PMMA7450LR2 Freescale Semiconductor, Inc, PMMA7450LR2 Datasheet - Page 18

• Manufacturer Part Number: PMMA7450LR2
• Description: ?2g/?4g/?8g Three Axis Low-g Digital Output Accelerometer
• Manufacturer: Freescale Semiconductor, Inc

$17: Interrupt latch reset (Read/Write
$18: Control 1 (Read/Write)
$19: Control 2 (Read/Write)
18
MMA7450L
DFBW
CLR_INT1
1: Clear “INT1” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” reg-
ister setting.
0: Do not clear “INT1” LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register.
CLR_INT2
1: Clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” reg-
ister setting.
0: Do not clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register.
INTPIN
0: INT1 pin is routed to “INT1” register and INT2 pin is routed to “INT2” register.
1: INT2 pin is routed to “INT1” register and INT1 pin is routed to “INT2” register.
Note: Assigned to single pulse detection even if double
pulse detection is selected. “Double pulse detection se-
lected” means “Time window for 2
zero. When double pulse detection is selected, INT1 reg-
ister bit is not able to be cleared by setting CLR_INT1 bit.
It’s cleared by setting CLR_INT2 bit. In this case, setting
CLR_INT2 clears both INT1 and INT2 register bits and re-
set detecting operation itself.
XDA
1: X axis is disabled for detection.
0: X axis is enabled for detection.
YDA
1: Y axis is disabled for detection.
0: Y axis is enabled for detection.
LDPOL
0: Level detection polarity is positive and detecting condi-
tion is OR 3 axes.
1: Level detection polarity is negative detecting condition
is AND 3 axes.
D7
D7
D7
--
INTREG[1:0]
--
0
0
0
00
01
10
THOPT
D6
D6
--
0
--
0
D6
0
D5
D5
--
--
0
0
Single pulse detection (*Note)
ZDA
D5
0
“INT1” register bit
Pulse Detection
Level Detection
D4
D4
--
--
0
nd
0
YDA
D4
pulse” is not equal
0
D3
D3
--
0
--
0
XDA
D3
0
DRVO
D2
D2
--
0
0
INTREG[1] INTREG[0]
D2
0
CLR_INT2 CLR_INT1
“INT2” register bit
PDPL
D1
D1
Pulse Detection
Pulse Detection
Level Detection
0
ZDA
1: Z axis is disabled for detection.
0: Z axis is enabled for detection.
THOPT (This bit is valid for level detection only, not valid
for pulse detection)
DFBW
0: Digital filter band width is 62.5 Hz
1: Digital filter band width is 125 Hz
0
PDPOL
0: Pulse detection polarity is positive and detecting condi-
tion is OR 3 axes.
1: Pulse detection polarity is negative and detecting con-
dition is AND 3 axes.
DRVO
0: Standard drive strength on SDA/SDO pin
1: Strong drive strength on SDA/SDO pin
0: Threshold value is absolute only
1: Positive/Negative threshold value is available.
D1
0
LDPL
D0
D0
0
0
INTPIN
D0
0
Function
Function
Default
Default
Bit
Bit
Function
Default
Bit
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