ATF-521P8 Avago Technologies, ATF-521P8 Datasheet - Page 14

• Manufacturer Part Number: ATF-521P8
• Description: Atf-521p8 Gaas Field Effect
• Manufacturer: Avago Technologies

14
ATF-521P8 Applications Information
Description
Avago Technologies' ATF‑521P8 is an enhancement
mode PHEMT designed for high linearity and medium
power applications. With an OIP3 of 42 dBm and a 1dB
compression point of 26 dBm, ATF‑521P8 is well suited
as a base station transmit driver or a first or second
stage LNA in a receive chain. Whether the design is for a
W‑CDMA, CDMA, or GSM basestation, this device deliv‑
ers good linearity in the form of OIP3 or ACLR, which is
required for standards with high peak to average ratios.
Application Guidelines
The ATF‑521P8 device operates as a normal FET requir‑
ing input and output matching as well as DC biasing.
Unlike a depletion mode transistor, this enhancement
mode device only requires a single positive power sup‑
ply, which means a positive voltage is placed on the
drain and gate in order for the transistor to turn on. This
application note walks through the RF and DC design
employed in a single FET amplifier. Included in this de‑
scription is an active feedback scheme to accomplish
this DC biasing.
RF Input & Output Matching
In order to achieve maximum linearity, the appropriate
input (Γ
sented to the device. Correctly matching from these
impedances to 50Ωs will result in maximum linearity.
Although ATF‑521P8 may be used in other impedance
systems, data collected for this data sheet is all refer‑
enced to a 50Ω system.
The input load pull parameter at 2 GHz is shown in Fig‑
ure 1 along with the optimum S11 conjugate match.
Figure 1. Input Match for ATF-521P8 at 2 GHz.
Figure 1. Input Match for ATF-521P 8
Thus, it should be obvious from the illustration above
that if this device is matched for maximum return loss
i.e. S11*, then OIP3 will be sacrificed. Conversely, if ATF‑
521P8 is matched for maximum linearity, then return
loss will not be greater than 10 dB. For most applica‑
tions, a designer requires VSWR greater than 2:1, hence
S11
*
s
) and output (Γ
Γ
S
L
) impedances must be pre‑
GHz.
limiting the input match close to S11*. Normally, the in‑
put return loss of a single ended amplifier is not critical
as most basestation LNA and driver amplifiers are in a
balanced configuration with 90° (quadrature) couplers.
Proceeding from the same premise, the output match
of this device becomes much simpler. As background
information, it is important to note that OIP3 is largely
dependant on the output match and that output return
loss is also required to be greater than 10 dB. So, Figure
2 shows how both good output return loss and good
linearity could be achieved simultaneously with the
same impedance point.
Of course, these points are valid only at 2 GHz, and
other frequencies will follow the same design rules but
will have different locations. Also, the location of these
points is largely due to the manufacturing process and
partly due to IC layout, but in either case beyond the
scope of this application note.
Figure 2. Output Match at 2 GHz.
Figure 2. Output Match
Once a designer has chosen the proper input and out‑
put impedance points, the next step is to choose the
correct topology to accomplish this match. For example
to perform the above output impedance transformation
from 50Ω to the given load parameter of 0.53∠‑176°,
two possible solutions exist. The first potential match
is a high pass configuration accomplished by a shunt
inductor and a series capacitor shown in Figure 3 along
with its frequency response in Figure 4.
RF
Figure 3. High Pass Circuit Topology.
in
Γ
C1
S22*
L
L1
RF
ou t
at 2 GHz.