EM65570 ELAN Microelectronics Corp, EM65570 Datasheet - Page 70
EM65570
Manufacturer Part Number
EM65570
Description
68com / 98seg 65k Color Stn Lcd Driver
Manufacturer
ELAN Microelectronics Corp
Datasheet
1.EM65570.pdf
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EM65570
68COM/ 98SEG 65K Color STN LCD Driver
64 x
8.2.7 Power Control Register
(At the time of reset: {AMPON, HALT, DCON, ACL} = 0H, read address: 9H)
ACL
The internal circuit can be initialized as follows:
ACL = “0”: Normal operation
ACL = “1”: Initialization ON
When the reset operation begins internally after the ACL register is set to “1,” the ACL
register is automatically cleared to “0.” The internal reset signal is generated with a
clock (built-in oscillation circuit or CK input) for the display. Therefore, install at least
two cycles for the WAIT period for the clock display. After the WAIT period elapsed, the
next operation is processed.
DCON
Sets ON/OFF the internal booster circuit:
DCON = “0”: Booster circuit OFF
DCON = ”1”: Booster circuit ON
D7
1
When each AX exceed AE, increment AY
AX:
AY:
Address
Address
START
START
D6
0
Transition of AX and AY Register
5. The following shows address increment in window function access.
Under each operation mode, the following increment operation is performed:
D5
0
When gradation display mode and 8-bit access are selected, address is
incremented as described above.
When gradation display mode and 16-bit access are selected, the following
increment processing occurs:
1) Accessing the RAM after every two bytes are accessed.
2) The X-addresses increments in the order of 00H, 01H,…2FH, and 30H.
Address+1
Address+1
START
START
D4
1
AMPON HALT DCON ACL
D3
D2
Address
Address
END
END
D1
(This specification is subject to change without further notice)
D0
Product Specification (V1.0) 09.05.2005
CSB RS RDB WRB RE2 RE1 RE0
0
Transition of X and Y Address
Same as AX and AY register
1
1
0
0
0
0
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