PN512 NXP Semiconductors, PN512 Datasheet - Page 11

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PN512

Manufacturer Part Number
PN512
Description
Transmission Module
Manufacturer
NXP Semiconductors
Datasheet

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124533
Product short data sheet
Fig 6. Data Coding and framing according to ISO 14443A
Current ISO14443 Framing for Type A for 106 kBaud
MIFARE Higher Baudrate Framing for 212, 424 kBaud
8.1.1.1 Data Coding and framing according to ISO 14443A/Mifare
Burst of 32
sub-carrier
clocks
Start
Start
Table 5.
The contactless UART of PN512 and a dedicated external host controller are required to
handle the complete Mifare/ISO 14443A/Mifare protocol.
The internal CRC co-processor calculates the CRC value according to the definitions
given in the ISO 14443A part 3 and handles parity generation internally according to the
transfer speed.
Communication
direction
PN512 → PICC
(send data from
the PN512 to a
card)
PICC → PN512
(receive data
from a card)
Start Bit is "1"
Start Bit is "0"
8 bit data
8 bit data
Communication overview for ISO 14443A/Mifare reader/writer
transfer speed
Modulation on
reader side
bit coding
Bitlength
modulation on
card side
subcarrier
frequency
bit coding
Rev. 3.3 — 13 June 2007
Par.
Par.
odd
odd
ISO 14443A/Mifare
106 kbit/s
100% ASK
Modified Miller coding
(128/13.56) μs
subcarrier load
modulation
13.56 MHz/16
Manchester coding
8 bit data
8 bit data
odd
Par.
odd
Par.
Mifare Higher transfer speeds
212 kbit/s
100% ASK
Modified Miller
coding
(64/13.56) μs
subcarrier load
modulation
13.56 MHz/16
BPSK
Even parity at the
end of the frame!
8 bit data
8 bit data
Transmission Module
© NXP B.V. 2007. All rights reserved.
424 kbit/s
100% ASK
Modified Miller
coding
(32/13.56) μs
subcarrier load
modulation
13.56 MHz/16
BPSK
even
Par.
Par.
odd
PN512
11 of 23

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