CY25200 Cypress Semiconductor Corporation., CY25200 Datasheet - Page 4

• Manufacturer Part Number: CY25200
• Description: Programmable Spread Spectrum Clock Generator For Emi Reduction
• Manufacturer: Cypress Semiconductor Corporation.

Product Functions
Control Pins (CP0, CP1, CP2 and CP3)
There are four control signals available through programming of
pins 4, 10, 14, and 15.
CP0 (pin 4) and CP1 (pin10) are specifically designed to function
as control pins. However pins 14 (SSCLK5/REFOUT/CP2) and
15 (SSCLK6/REFOUT/CP3) are multi-functional and are
programmed to be a control signal or an output clock (SSCLK or
REFOUT). All of the control pins, CP0, CP1, CP2, and CP3 are
programmable and are programmed to have only one of the
following functions:
■
■
■
■
The last control signal is the power down (PD#) that is imple-
mented only through programming CP0 or CP1 (CP2 and CP3
cannot be programmed as PD#). Here is an example with three
control pins:
■
■
■
■
■
■
The pinout for the above example is shown in
The CLKSEL control pin enables the user to change the output
frequency from one frequency to another (for example,
frequency A to frequency B). These must be related frequencies
that are derived off of a common VCO frequency. For instance,
33.333 MHz and 66.666 MHz are both derived from a VCO of
400 MHz and dividing it down by 12 and 6 respectively.
Document #: 38-07633 Rev. *D
Output Enable (OE)—if OE = 1, all the SSCLK or REFOUT
outputs are enabled.
SSON, Spread spectrum control—1 = spread on and
0 = spread off.
CLKSEL—SSCLK output frequency select
PD#, Active Low—if PD# = 0, all the outputs are three-stated
and the part enters a low power state.
CLKIN = 33 MHz
SSCLK1/2/3/4 = 100 MHz with ±1% spread
SSCLK 5 = REFOUT(33 MHz)
CP0 (Pin 4) = PD#
CP1 (Pin 10) = OE
CP3 (pin 15) = SSON
33.0MHz
100MHz
100MHz
AVDD
AVSS
VSSL
VDD
Figure 2. Pin Diagram
PD#
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
SSON
REFOUT(33.0MHz)
VSS
100MHz
VDDL
OE
100MHz
Figure
2.
Table 4
shows an example of how this is implemented. The VCO
frequency range is 100–400MHz. The CY25200 has two
separate dividers, Divider 1 and Divider 2. These two are loaded
to have any number between 2 and 130 providing two different
but related frequencies as explained above.
In the above example SSCLK5 (pin 14) and SSCLK6 (pin 15) are
used as output clocks. However, they can also be used as control
signals. See
Input Frequency (XIN, pin 1 and XOUT, pin 16)
The input to the CY25200 is a crystal or a clock. The input fre-
quency range for crystals is 8 to 30 MHz, and for clock signal is
8 to 166 MHz.
C
The load capacitors at pin 1 (C
programmed from 12 pF to 60 pF with 0.5 pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
The required values of C
(CL) is calculated using the following formula:
C
Where C
manufacturer and C
For example, if a fundamental 16 MHz crystal with C
used and C
C
If using a driven reference clock, set C
imum value 12 pF.
Output Frequency (SSCLK1 through SSCLK6
Outputs)
All of the SSCLK outputs are produced by synthesizing the input
reference frequency using a PLL and modulating the VCO
frequency. SSCLK[1:4] is programmed to be only output clocks
(SSCLK). SSCLK5 and SSCLK6 are also programmed to
function the same as SSCLK[1:4] or a buffered copy of the input
reference (REFOUT) or they are programmed to be a control pin
as discussed in the control pins section. To use the 2.5V output
drive option on SSCLK[1:4], VDDL must be connected to a 2.5V
power supply (SSCLK[1:4] outputs are powered by VDDL).
When using the 2.5V output drive option, the maximum output
frequency on SSCLK[1:4] is 166 MHz.
Spread Percentage (SSCLK1 through SSCLK6
Outputs)
The SSCLK frequency is programmed at any percentage value
from ±0.25% to ±2.5% for center spread and from –0.5% to
–5.0% down spread.
Frequency Modulation
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if a
higher modulation frequency is required.
XIN
XIN
XIN
= C
= C
and C
XOUT
XOUT
L
is the crystal load capacitor as specified by the crystal
P
XOUT
Figure 3
is 2 pF, C
= (2 x 16) – 2 = 30 pF.
= 2C
(pin 1 and pin 16)
L
P
– C
for the pinout.
is the parasitic PCB capacitance.
XIN
XIN
P
and C
and C
XOUT
XIN
XOUT
) and pin 16 (C
XIN
is calculated as:
for matching crystal load
and C
XOUT
CY25200
Page 4 of 12
L
to the min-
of 16 pF is
XOUT
) are
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