S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 59

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
HYPK[1:0]
CTRAP
HYBWR
PED
RGBH
UNIT
Index
0x0F
Mnemonic
LUMA
ELECTRONICS
Luminance horizontal peaking control around 3 MHz.
0
1
2
3
Chroma trap (notch filter) in the luma path.
0
1
Luminance horizontal bandwidth reduction control.
0
1
Enable gain correction for 7.5 blank-to-black setup (pedestal).
0
1
High gain to produce full range Y for 0% (or 7.5% if PED = 1) to 100% input.
0
1
When PED and RGBH are both set to a “1”, setting this bit to a “1” produces a unit gain for
CCIR 601 digital input (INPSL[1:0] = 1).
0
1
bit 7
0
Less than nominal peaking.* (0 dB)
Nominal peaking. (2 dB)
Increased peaking. (4 dB)
Maximum peaking. (8 dB)
No chroma trap. This mode is recommended for S-video or component video input.*
Chroma trap is enabled.
Full bandwidth.*
Reduced bandwidth.
No pedestal. 0% = Y code 16. 100% = Y code 235.*
Gain adjusted for 7.5% blank-to-black setup (pedestal). 7.5% = Y code 16. 7.5% -
100% input produce Y code 16 - 235.
Black (0% or 7.5%) to peak white(100%) input produce Y code 16 to 235.*.
Black (0% or 7.5%) to peak white(100%) input produce Y code 0 to 255.
Luma DC gain is controlled by PED and RGBH as described for each bit.*
Luma DC gain is unity for CCIR 601 digital input.
UNIT
bit 6
Luma Control Register
RGBH
bit 5
bit 4
PED
HYBWR
bit 3
CTRAP
bit 2
MULTIMEDIA VIDEO
bit 1
HYPK[1:0]
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bit 0
7/18/03