S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 51

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
Index
IFMT
MNFMT
PIXSEL
XT24
HFSEL[1:0]
VSE
POWDN
01h
Mnemonic
CMDA
ELECTRONICS
Manual video input standard select. Standard selection can be controlled automatically if
MNFMT=0.
0
1
Manual input format control override. When this bit is 1 the IFMT bit is enabled.
0
1
Select pixel sampling rate.
0
1
Select the external clock reference frequency.
0
1
Horizontal tracking loop frequency select.
0
1
2
3
Change the vertical end location of the VS.
0
1
Power down mode.
0
1
POWDN
bit 7
Chip is forced to assume input is 50 Hz.*
Chip is forced to assume input is 60 Hz.
The chip determines the input video standard based on the detected field rate:*
NTSC if 60 Hz.
PAL/SECAM if 50 Hz.
Input video standard is selected with the IFMT bit.
Output data is at square pixel rate.
Output data is at CCIR 601 rate.*
External clock is 26.8 MHz.
External clock is 24.576 MHz.*
Force loop to very fast.
Force loop to fast.
Force loop to VCR time constant.*
Force loop to TV time constant.
Line 10/10.5.*
Line 9/9.5.
Normal operation.*
All chip functions except microprocessor interface and CK/CK2 generation are
disabled. The output of the CK/CK2 pins retains the most recent frequency when
the power down mode is enabled.
bit 6
VSE
Control Register A
bit 5
HFSEL[1:0]
bit 4
XT24
bit 3
PIXSEL
bit 2
MULTIMEDIA VIDEO
MNFMT
bit 1
PAGE 51 OF 95
IFMT
bit 0
7/18/03