PR31500 NXP Semiconductors, PR31500 Datasheet

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PR31500

Manufacturer Part Number
PR31500
Description
Poseidon Embedded Processor
Manufacturer
NXP Semiconductors
Datasheet
Philips
Semiconductors
Preliminary specification
Version 0.1
MIPS
PR31500
Poseidon embedded processor
INTEGRATED CIRCUITS
1996 Sep 24

Related parts for PR31500

PR31500 Summary of contents

Page 1

... MIPS PR31500 Poseidon embedded processor Preliminary specification Version 0.1 Philips Semiconductors INTEGRATED CIRCUITS 1996 Sep 24 ...

Page 2

... PR31500 Processor is a single-chip, low-cost, integrated embedded processor consisting of MIPS R3000 core and system support logic to interface with various types of devices. PR31500 consists of a MIPS R3000 RISC CPU with 4 KBytes of instruction cache memory and 1 KByte of data cache memory, plus integrated functions for interfacing to numerous system components and external I/O modules ...

Page 3

... Sep 24 Data Addr System Interface Unit (SIU) Module Arbitration/DMA/AddrDecode CHI Module IR Module UART Module (dual UART) SPI Module Power Module Interrupt Module Figure 1. PR31500 Block Diagram 3 Preliminary specification MIPS PR31500 Data to Memory Addr Control to high speed serial to IR ...

Page 4

... ROM, SRAM, Flash available for external port expansion registers supports identical full PCMCIA ports – PR31500 and UCB1100 provide the control signals and accepts the status signals which conform to the PCMCIA version 2.01 standard – appropriate connector keying and level-shifting buffers required for 3 ...

Page 5

... DMA support for fetching image data from video buffer Little/Big Endian Configuration The PR31500 can be configures as a Big Endian Little Endian processor based on the /LB endian pin at power-up. The byte ordering is as follows: LITTLE ENDIAN ...

Page 6

... Philips Semiconductors Poseidon embedded processor Figure 2 shows a typical system block diagram cosisting of PR31500 and UCB1100 for a total system solution. 3.3V SYSCLK R3000 RISC CPU core PR31500 TLB LCD IR ISDN High speed serial port or other peripherals Touchscreen (Resistive) Phone Jack 1996 Sep 24 1–2 PCMCIA Slots Î ...

Page 7

... D(21) [D(13)] VDAT(1) 151 V DD VDAT(2) 152 D(20) [D(12)] VDAT(3) 153 D(19) [D(11)] V 154 IO(1) 155 D(18) [D(10)] V 156 Preliminary specification MIPS PR31500 Pin Function 157 D(17) [D(9)] 158 V SS 159 D(16) [D(8)] 160 V DD 161 162 /CS0 163 /RD 164 V SS 165 V DD 166 /DGRNT 167 /DREQ 168 ALE 169 ...

Page 8

... Pins The PR31500 PROCESSOR contains 208 total pins, consisting of 136 signal pins, 4 spare pins, 34 power pins, and 34 ground pins. Of the 136 signal pins them are multi-function and can be independently programmed either as IO ports or for an alternate standard/normal function port, any of these pins can be programmed as an input or output port, with the capability of generating a separate positive and negative edge interrupt ...

Page 9

... This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes output, this pin allows PR31500 to be the master CHI sync source input, this pin allows an external peripheral to be the master CHI sync source and the PR31500 CHI module will slave to this external sync ...

Page 10

... VSTANDBY through an external pull-up resistor. 87 /PON I This pin serves as the Power On Reset signal for PR31500. This signal must remain low when VSTANDBY is asserted until VSTANDBY is stable. Once VSTANDBY is asserted, this signal should never go low unless all power is lost in the system. Power Supply Pins ...

Page 11

... Reserved. 32, 31 – Reserved. Power Supply Pins V (34 each) +3.3V These pins are the power pins for PR31500 and should be connected to the digital +3.3V power DD supply VSTANDBY. V (34 each) GND These pins are the ground pins for PR31500 and should be connected to digital ground. SS NOTE: For some vendor-dependent implementations of PR31500, pin 131 may be used for a filter capacitor for the SYSCLK oscillator (capacitor connected between pin 131 and digital ground) ...

Page 12

... 3. 16mA – 3. –24mA V – 24mA – MAX Preliminary specification MIPS PR31500 LIMITS UNIT V – 0 – –55 to +125 LIMITS UNIT UNIT TYP MAX 3.3 3.6 V – – LIMITS UNIT ...

Page 13

... Philips Semiconductors Poseidon embedded processor AC ELECTRICAL CHARACTERISTICS 0.8V DELAY 2.2V OUTPUTS 0.8V 0.8V CC INPUTS 0.2V CC Figure 3. PR31500 Timing – Definition of AC Specification 1996 Sep 24 2.0V SETUP HOLD 2.2V 2.2V 0.8V 0.8V 13 Preliminary specification MIPS PR31500 SN00165 ...

Page 14

... C IN OUT PARAMETER PARAMETER C32KIN C32KOUT 79 80 RECOMMENDED 32kHz CRYSTAL KYOCERA CORPORATION: KF-38G XTAL OUT PARAMETER PARAMETER 14 Preliminary specification MIPS PR31500 SN00166 RECOMMENDED VALUE UNIT UNIT MIN. MAX. 8.25 10 MHz TBD TBD SN00167 RECOMMENDED VALUE UNIT UNIT MIN. MAX. ...

Page 15

... Rising 1.5 Falling 1.5 Rising 1.5 Falling 1.5 Rising 1.5 Falling 1.5 Rising 1.5 Falling 1.5 Rising – Falling – – 2 – 1 – 1 – 1.5 – Preliminary specification MIPS PR31500 UNIT UNIT MAX – ns – ns – 1 ...

Page 16

... Philips Semiconductors Poseidon embedded processor MEMORY INTERFACE TIMING DIAGRAMS DCLKOUT MEMORY OUTPUTS DCLKIN MEMORY INPUTS DCLKOUT DCLKIN 1996 Sep Figure 1. Memory Output and Clock Timing 5 6 Figure 2. Memory Input Timing 7 Figure 3. DCLKOUT to DCLKIN 16 Preliminary specification MIPS PR31500 SN00168 SN00169 SN00170 ...

Page 17

... Falling – Rising – Falling – – 20 – 20 – 20 – 20 – 20 – 20 – 20 – 20 – 20 – 20 – 20 – Preliminary specification MIPS PR31500 UNIT UNIT MAX – ns – ns – ...

Page 18

... CHI INPUTS CHICLK CHI OUTPUTS Figure 6. CHI Output and Clock Timing (CHITXEDGE = 0) CHICLK CHI INPUTS 1996 Sep Figure 5. CHI Input Timing (CHIRXEDGE = Figure 7. CHI Input Timing (CHIRXEDGE = 0) 18 Preliminary specification MIPS PR31500 SN00171 SN00172 SN00173 SN00174 ...

Page 19

... Rising Falling Rising Falling Rising Falling – – Figure 8. SIB CLK Timing Figure 9. SIB Timing 19 Preliminary specification MIPS PR31500 LIMITS UNIT UNIT MIN MAX 20 – – – ns – – – – ...

Page 20

... Rising Falling Rising Falling – – – – Figure 10. SPI Timing (PHAPOL = Figure 11. SPI Timing (PHAPOL = 0) 20 Preliminary specification MIPS PR31500 LIMITS UNIT UNIT MIN MAX 120 – ns 120 – ns 250 – ns – ns – ns – ns – ...

Page 21

... Figure 13. Video Data Timing, 4 Bit Split LCD and 8 Bit Non-Split LCD 1996 Sep 24 RISING/FALLING RISING/FALLING – – – – – – – Figure 12. Video Timing, 4 Bit Non-Split LCD Preliminary specification MIPS PR31500 LIMITS UNIT UNIT MIN MAX 100 1600 ns 100 3200 ns 100 3200 ns 100 3200 ns – ...

Page 22

... ITEM ITEM PARAMETER PARAMETER 1 /CPURES low time /CPURES 1996 Sep 24 RISING/FALLING RISING/FALLING – – Figure 14. RISING/FALLING RISING/FALLING – 1 Figure 15. 22 Preliminary specification MIPS PR31500 LIMITS UNIT UNIT MIN MAX 50 – – s SN00181 LIMITS UNIT UNIT MIN MAX 10 – ns SN00182 ...

Page 23

... Philips Semiconductors Poseiden embedded processor LQFP208: 208-PIN PLASTIC LOW PROFILE QUAD FLAT PACKAGE 156 157 208 1 1.25 TYP. 0.17 +0.03 –0.05 UNIT = mm (Drawing not to scale) 1996 Sep 24 +0.05 0.22 0.5 –0.04 0.1 29.00 0.2 (0.5) 0–10 0.45–0.75 23 Preliminary specification MIPS PR31500 105 104 30.00 0.2 28.00 0 0.1 ...

Page 24

... Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. © Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. 24 Preliminary specification MIPS PR31500 ...

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