LMX2324 National Semiconductor Corporation, LMX2324 Datasheet - Page 8

• Manufacturer Part Number: LMX2324
• Description: Pllatinum? 2.0 Ghz Frequency Synthesizer For Rf Personal Communications
• Manufacturer: National Semiconductor Corporation

www.national.com
Register
Divide
2.0 Programming Description
2.3 N REGISTER
If the address bit is LOW (ADDR=0) when LE is transitioned high, data is transferred from the 18-bit shift register into the 17-bit
N register. The N register consists of the 5-bit swallow counter (A counter), the 10-bit programmable counter (B counter) and the
control word. Serial data format is shown below in tables 2.3.1 and 2.3.2. The pulse swallow function which determines the divide
ratio is described in section 2.3.3. Data is clocked into the shift register MSB first.
2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter)
Notes: Swallow Counter Value: 0 to 31
NB_CNTR ≥ NA_CNTR
2.3.2 10-Bit Programmable Counter Divide Ratio (B Counter)
Notes: Divide ratio: 3 to 1,023 (Divide ratios less than 3 are prohibited)
NB_CNTR ≥ NA_CNTR
2.3.3 Pulse Swallow Function
The N divider counts such that it divides the VCO RF frequency by (P+1) A times, and then divides by P (B - A) times. The B value
(NB_CNTR) must be ≥ 3. The continuous divider ratio is from 992 to 32,767. Divider ratios less than 992 are achievable as long
as the binary counter value is greater than the swallow counter value (NB_CNTR ≥ NA_CNTR).
f
N = (P x B) + A
f
f
R:
N:
B:
A:
P:
2.3.4 CTL_WORD
Swallow Count
Ratio
1023
VCO
VCO
OSC
N
3
4
•
: Output frequency of external voltage controlled oscillator (VCO)
: Output frequency of the external reference frequency oscillator
= N x (f
Preset divide ratio of binary 10-bit programmable reference counter (2 to 1023)
Preset divide ratio of main 15-bit programmable integer N counter (992 to 32,767)
Preset divide ratio of binary 10-bit programmable B counter (3 to 1023)
Preset value of binary 5-bit swallow A counter (0 ≤ A ≤ 31, A ≤ B)
Preset modulus of dual modulus prescaler (P=32)
MSB
(A)
N16 N15 N14
31
17
0
1
•
OSC
N16
16
0
0
1
•
/R)
15
N13
14
N15
MSB
0
0
1
•
N6
0
0
1
•
N12
13
CNT_RST
NB_CNTR[9:0]
N14
0
0
1
•
N1
N11
12
SHIFT REGISTER BIT LOCATION
N13
0
0
1
N5
•
0
0
1
(Continued)
•
NB_CNTR[10:0]
N10
11
Data Field
N12
0
0
1
8
•
N9 N8 N7
10
NA_CNTR[4:0]
9
N4
N11
0
0
1
•
0
0
1
•
8
N6
7
PWDN
N0
N10
NA_CNTR[4:0]
0
0
1
•
N5 N4 N3 N2
6
5
N3
0
0
1
•
4
N9
0
1
1
•
3
LSB
CTL_WORD[1:0]
N1
2
N8
1
0
1
•
N2
N0
0
1
1
•
1
N7
1
0
1
•
ADDR
LSB
Field
0
0