LMX2324 National Semiconductor Corporation, LMX2324 Datasheet - Page 7

• Manufacturer Part Number: LMX2324
• Description: Pllatinum? 2.0 Ghz Frequency Synthesizer For Rf Personal Communications
• Manufacturer: National Semiconductor Corporation

Register
CP_TRI
PD_POL
TEST
R Divider Output
N Divider Output
Divide
2.0 Programming Description
2.2 R REGISTER
If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into the 14-bit R
register. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide ratio is programmed using
the bits R_CNTR as shown in table 2.2.1. The ratio must be ≥ 2. The PD_POL, CP_TRI and TEST bits control the phase detector
polarity, charge pump TRI-STATE, and test mode respectively, as shown in 2.2.2. The RS bit is reserved and should always be
set to zero. X denotes a don’t care condition. Data is clocked into the shift register MSB first.
2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter)
Notes: Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited)
R_CNTR — These bits select the divide ratio of the programmable reference dividers.
2.2.2 R Register Truth Table
If the test mode is NOT activated (R[13]=0), the charge pump is active when CP_TRI is set LOW. When CP_TRI is set HIGH, the
charge pump output and phase comparator are forced to a TRI-STATE condition. This bit must be set HIGH if the test mode is
ACTIVATED (R[13]=1).
If the test mode is NOT activated (R[13]=0), PD_POL sets the VCO characteristics to positive when set HIGH. When PD_POL
is set LOW, the VCO exhibits a negative characteristic where the VCO frequency decreases with increasing control voltage.
If the test mode is ACTIVATED (R[13]=1), the outputs of the N and R counters are directed to the CP
The PD_POL bit selects which counter output according to Table 2.2.3.
2.2.3 Test Mode Truth Table (R[13] = 1)
Ratio
1,023
2
3
•
R
Bit
MSB
R16 R15 R14
17
CP
X
R9
0
0
1
•
o
Output
16
X
R[10]
R[11]
R[13]
15
X
R8
0
0
1
•
TEST
R13
14
Location
R12
RS
R7
13
0
0
1
•
POL
PD_
R11
12
R6
Charge Pump
TRI-STATE
Phase Detector Polarity
Test Mode Bit
0
0
1
•
(Continued)
SHIFT REGISTER BIT LOCATION
CP_TRI R[10]
R_CNTR[9:0]
CP_
R10
Function
TRI
11
R5
Data Field
0
0
1
1
1
•
7
R9
10
R8
9
R4
0
0
1
•
Normal Operation
Negative
Normal Operation
R7 R6 R5
8
7
R3
0
0
1
•
R_CNTR[9:0]
6
0
R4
5
R2
R3
0
0
1
•
4
o
PD_POL R[11]
output to allow for testing.
TRI-STATE
Positive
Test Mode
R2
3
0
1
R1
R1
1
1
1
•
2
1
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R0
1
R0
0
1
1
•
ADDR
LSB
Field
0
1