LMX2485 National Semiconductor Corporation, LMX2485 Datasheet - Page 21

• Manufacturer Part Number: LMX2485
• Description: 50 Mhz - 3.0 Ghz High Performance Delta-sigma Low Power Dual Pllatinum 50 Mhz - 3.0 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 800 Mhz Integer Pll
• Manufacturer: National Semiconductor Corporation

Functional Description
1.7 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of e. To indicate a locked state
(Lock = HIGH) the phase error must be less than the e RC
delay for 5 consecutive reference cycles. Once in lock (Lock
= HIGH), the RC delay is changed to approximately δ. To
indicate an out of lock state (Lock = LOW), the phase error
must become greater δ. The values of e and δ are dependent
on which PLL is used and are shown in the table below:
When the PLL is in the power down mode and the Ftest/LD
pin is programmed for the lock detect function, it is forced
LOW. The accuracy of this circuit degrades at higher com-
parison frequencies. To compensate for this, the DIV4 word
should be set to one if the comparison frequency exceeds 20
MHz. The function of this word is to divide the comparison
frequency presented to the lock detect circuit by 4. Note that
if the MUX[3:0] word is set such as to view lock detect for
both PLLs, an unlocked (LOW) condition is shown whenever
either one of the PLLs is determined to be out of lock.
(Continued)
CE Pin RF_PD
High
High
High
Low
PLL
RF
IF
X
X
0
1
Bit Enabled +
Write to RF
N Counter
10 ns
15 ns
ATPU
Yes
No
No
e
X
(Note 9)
( Asynchronous )
(Asynchronous)
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PLL State
20 ns
30 ns
δ
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