CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 34

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

IDE Interface Signals (continued)
USB Interface Signals
Miscellaneous Signals
Name
BLKIDE
Name
USB_CLK
USB_D1+,
USB_D1–
USB_D2+,
USB_D2–
Name
ROMCS
/ROMMODE
VBATT
+5V
+3.3V
GND
I/O
O
I/O
I
I/O
I/O
I/O
I/O
I
I
I
I
PRELIMINARY
Description
Block IDE: This signal may be used in conjunction with an external Quad OR gate to
block the IDE chip selects to the IDE drives during ISA transfers. This prevents older
IDE devices from hanging if multiple IDE chip selects are asserted. Newer drives will
not have a problem because IDE chip selects will only be sampled when an IDE COM-
MAND signal (IDEIOW or IDEIOR) is asserted.
Description
USB 48MHz Clock Input
USB port 1: This signal pair comprises the differential signal for USB port 1.
USB port 2: this signal pair comprises the differential signal for USB port 2.
Description
System ROM Chip Select: This signal is used to enable the on-board BIOS ROM.
At power-up, this signal acts as ROMMODE. ROMMODE is used in conjunction with
ROMS0 (GTA20) and ROMS1 (IGNNE) to implement boot-block Flash recovery straps.
The strapping is defined as follows:
ROMMODE
Battery Backup Power: This pin should be connected directly to a battery-driven power
source. Used to retain and maintain RTC functionality when the main power supply is
disconnected.
V
within the proper operating limits.
3.3-Volt V
within the proper operating limits.
GROUND: These are the 0V power supply pins for the device. They should be main-
tained within the proper operating limits.
CC
: These are the +5V power supply pins for the device. They should be maintained
1
0
0
0
0
CC
: This is the +3.3V power supply pin for the device. It should be maintained
ROMS0
1
X
1
0
0
34
ROMS1
X
1
0
1
0
Result
No ROM address bits are
inverted. (EPROM or boot-
block recovery mode).
ROM address bit 16 is inverted
(Normal operation w/ 16Kx8
boot-block Flash)
ROM address bit 17 is inverted
(Normal operation with 32Kx8
boot-block Flash)
ROM address bit 18 is inverted
(Normal operation with 64Kx8
boot-block Flash)
ROM address bit 15 is inverted
(Normal operation with 8Kx8
boot-block Flash)
CY82C693UB