L9805 STMicroelectronics, L9805 Datasheet
L9805
Related parts for L9805
L9805 Summary of contents
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... Master Reset, Power-On Reset, Low Voltage Reset July 2001 This is preliminary information on a new product now in development. Details are subject to change without notice. PROUCT PREVIEW HiQUAD-64 ORDERING NUMBER: L9805 70m DMOS H-bridge. 8-bit Data Manipulation 63 basic Instructions and 17 main Addressing Modes ...
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... L9805 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 OTP, ROM AND EPROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 PIN OUT 1.4 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 OSCILLATOR SAFEGUARD (DCSR ...
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... CAN Transceiver Disabling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.8 POWER BRIDGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.8.4 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.8.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.9 EEPROM (EEP 5.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.9.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 POWER CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table of Contents L9805 3/103 ...
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... L9805 7.3 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4 APPLICATION DIAGRAM EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.6 CONTROL TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7 OPERATING BLOCK ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . 100 4/103 ...
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... UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo cur- rent recommended to keep the L9805 device out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Ex- tended exposure to room level fluorescent lighting may also cause erasure ...
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... L9805 Figure 1. L9805 Block Diagram OSCIN OSCOUT OSC SAFEGUARD NRESET CONTROL 8-BIT CORE VPP/TM ROM/OTP/EPROM RAM 256B EEPROM 128B WATCHDOG CONTROLLER CAN_H TRANSCEIVER CAN_L 6/103 Internal CLOCK PREREGULATOR OSC POWER SUPPLY ALU POWER BRIDGE 16K TEMP SENSOR 10-bit ADC CAN PWM 1 ...
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... PA0/OCMP2_1 8 VPP/TM 9 VDD 10 OSCIN 11 OSCOUT 12 GND VBL 15 VBL 16 VBL L9805 NU 51 PB1/EXTCLK_2 PWMO 47 PWMI 46 NRESET 45 CAN_H 44 CAN_L 43 GND 42 VDD 41 VB2 40 VB1 39 VBR 38 VBR 37 VBR 36 NU ...
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... L9805 1.4 PIN DESCRIPTION AD2-AD4: Analog input to ADC. PA0/OCMP2_1-PA1/OCMP1_1: I/Os or Output compares on Timer 1. Alternate function software selectable (by setting OC2E or OC1E in CR2 reg- ister: bit 0031h). When used as an alter- nate function, this pin is a push-pull output as re- quested by Timer 1. Otherwise, this pin is a trig- gered floating input or a push-pull output ...
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... Miscellaneous Register .. Bridge Control Status Register .. Dedicated Control Status Register RESERVED .. Watchdog Control Register .. Watchdog Status Register .. EEPROM Control register EPROM Control register 1 EPROM Control register 2 CRCL Test Register CRCH Test Register L9805 Reset Remarks Status 00h R/W 00h R/W 00h R/W Absent 00h R/W 00h R/W R/W ...
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... L9805 Register La- Address Block bel 0031h T1CR2 0032h T1CR1 0033h T1SR 0034h-0035h T1IC1HR T1IC1LR 0036h-0037h T1OC1HR T1OC1LR 0038h-0039h TIM1 T1CHR T1CLR 003Ah-003Bh T1ACHR T1ACLR T1IC2HR 003Ch-003Dh T1IC2LR 003Eh-003Fh T1OC2HR T1OC2LR 0040h 0041h T2CR2 0042h T2CR1 0043h T2SR 0044h-0045h T2IC1HR T2IC1LR 0046h-0047h ...
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... T0H 0C00h to EEPROM 128 0C7DH: T0L 0C7Fh bytes 0C7EH: VT0H 0C7FH: VT0L 0C80h to BFFFh C000 to User application code and data EPROM 16K FFDFh bytes FFE0h to (16384 bytes) Interrupt and Reset Vectors FFFFh RESERVED RESERVED L9805 Section 5.5.6) 11/103 ...
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... L9805 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU has a full 8-bit architecture. Six internal registers allow efficient 8-bit data manipulation. The CPU is capable of executing 63 basic instruc- tions and features 17 main addressing modes. 2.2 CPU REGISTERS The 6 CPU registers are shown in the program- ming model in Figure 2, on page 12. Following an ...
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... ALU occured during the last arithmetic operation. This bit is also affected during execution of bit test, branch, shift, rotate and store instructions CONDITION CODE ACCUMULATOR X INDEX REGISTER PCH PCL L9805 CONTEXT SAVED ON INTERRUPT LOWER ADDRESS HIGHER ADDRESS 13/103 ...
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... L9805 3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a Crystal or Ceramic res- onator external clock signal to drive the in- ternal oscillator. The internal clock (f rived from the external oscillator frequency (f The external Oscillator clock is first divided by 2, ...
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... The equivalent specification of the external clock source should be used instead New frequency active when Normal mode osc/4 & osc requested L9805 (see ). OXOV 1 0 Normal mode active (osc/4 - osc/8 stopped VR02062B 15/103 ...
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... L9805 3.2 OSCILLATOR SAFEGUARD The L9805 contains an oscillator safe guard func- tion. This function provides a real time check of the crystal oscillator generating a reset condition when the clock frequency has anomalous value < reset is generated. OSC low If f >f a reset is generated. OSC high, A flag in the Dedicated Control Status Register in- dicates if the last reset is a safeguard reset ...
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... The T6 bit can be used to generate a software re- set (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. WATCHDOG STATUS REGISTER (WDGSR) WATCHDOG CONTROL REGISTER (WDGCR) LSB 7-BIT DOWNCOUNTER CLOCK DIVIDER 12288 L9805 = 16 MHz) OSC WDG timeout period (ms) 98.3 1.54 WDGF 17/103 ...
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... L9805 WATCHDOG SYSTEM (Cont’d) The Watchdog delay time is defined by bits 5-0 of the Watchdog register; bit 6 must always be set in order to avoid generating an immediate reset. Conversely, this can be used to generate a soft- ware reset (bit bit 6 = 0). The Watchdog must be reloaded before bit 6 is dec- remented to “ ...
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... The selection issued from b3/b4 combination is applied to PA[0]..PA[7],PB0,PB1 external inter- rupt. The selection can be made only if I bit register is reset (interrupt enabled). b3, b4 can be written only when the Interrupt Mask (I) of the CC (Condition Code) register is set to 1. b5,b6,b7 = not used L9805 19/103 ...
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... L9805 3.5 RESET 3.5.1 Introduction There are four sources of Reset: – NRESET pin (external source) – Power-On Reset / Low Voltage Detection (Inter- nal source) – WATCHDOG (Internal Source) – SAFEGUARD (Internal source) The Reset Service Routine vector is located at ad- dress FFFEh-FFFFh. 3.5.2 External Reset The NRESET pin is both an input and an open- drain output with integrated pull-up resistor ...
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... Figure 9. Power Up/Down behaviour Reset ON V Reset OFF V Reset UD POR/LVD 5V Figure 10. Reset Block Diagram V DD Oscillator Signal 300K NRESET = undefined value CLK to ST7 Reset L9805 t t Internal RESET RESET Watchdog Reset Safeguard Reset POR/LVD Reset 21/103 ...
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... L9805 3.6 INTERRUPTS A list of interrupt sources is given in together with relevant details for each source. In- terrupts are serviced according to their order of pri- ority, starting with I0, which has the highest priori- ty, and so to I12, which has the lowest priority. The following list describes the origins for each in- terrupt level: – ...
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... INTERRUPTS (Cont’d) Figure 11. Interrupt Processing Flowchart INTERRUPT TRAP Y I BIT = 1 FETCH NEXT INSTRUCTION OF APPROPRIATE INTERRUPT SERVICE ROUTINE EXECUTE INSTRUCTION Note 1. See Table ONTO STACK SET I BIT TO 1 WITH APPROPRIATE INTERRUPT VECTOR L9805 PUSH PC,X,A,CC LOAD VR01172B 23/103 ...
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... L9805 3.7 POWER SAVING MODES 3.7.1 Introduction There are three Power Saving modes. The Slow Mode may be selected by setting the relevant bits in the Miscellaneous register as detailed in 3.4. Wait and Halt modes may be entered using the WFI and HALT instructions. 3.7.2 Slow Mode In Slow mode, the oscillator frequency can be di- vided rather than by 2 ...
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... ADC, voltage regulators, bus transceivers and power bridge. HALT INSTRUCTION OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT N RESET Y Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT L9805 OFF OFF OFF CLEARED SET 25/103 ...
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... L9805 4 VOLTAGE REGULATOR 4.1 Introduction The on chip voltage regulator provides two regu- lated voltage, nominally 5V both. VCC supplies ADC and the analog periphery and VDD supplies the microcontroller and logic parts. These voltage are available at pins VDD and VCC to supply ex- ternal components and connects a capacitors to optimize EMI performance ...
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... MAXVCC this value the VCC voltage starts falling down. Ex- ternal loads must be chosen taking in account this maximum current capability of the regulator. WARNING: The pin VB2 is not short circuit pro- tected so a short circuit on this pin will destroy the device. L9805 27/103 ...
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... L9805 5 ON-CHIP PERIPHERALS 5.1 I/O PORTS 5.1.1 Introduction The internal I/O ports allow the transfer of data through digital inputs and outputs, the interrupt generation coming from an I/O and for specific pins, the input/output of alternate signals for the on-chip peripherals (TIMERS...). Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output ...
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... ICAP2_2: Input Capture #2 push-pull/open drain Timer 2 Function Output Alternate ICAP1_2: Input Capture #1 push-pull/open drain Timer 2 EXTCLK_2: External Clock push-pull/open drain Timer 2 Not connected to pad PWMI: PWM input L9805 Interrupt wake-up interrupt (I0) wake-up interrupt (I0) wake-up interrupt (I0) wake-up interrupt (I0) wake-up interrupt (I0) wake-up interrupt (I0) ...
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... L9805 I/O PORTS (Cont’d) . Figure 15 Ports PA0-PA7, PB0-PB1 Alternate output DR latch DDR latch OR latch OR SEL DDR SEL DR SEL Alternate input from Interrupt other bits I 30/103 Alternate enable Alternate enable Pull-up condition Alternate 1 enable digital enable VDD P-BUFFER ...
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... Reset Value: 0000 0000 (00h) (input mode) 7 MSB 5.1.3.3 Option registers (PAOR) Port A: 0002h Read/Write Reset Value: 0000 0000 (00h) (no interrupt MSB LSB (PBOR) Port B: 0006h Read/Write Reset Value: 0000 0000 (00h) (no interrupt MSB LSB 0 LSB 0 LSB L9805 0 LSB 0 0 LSB 31/103 ...
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... L9805 5.2 16-BIT TIMER 5.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals ( input capture ) or generation two out- put waveforms ( output compare and PWM ). ...
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... COMPARE REGISTER REGISTER REGISTER 1 2 TIMER INTERNAL BUS 16 16 OUTPUT COMPARE CIRCUIT OLVL2 IEDG1 OLVL1 OC1E OC2E OPM CR1 L9805 INPUT CAPTURE REGISTER EDGE DETECT ICAP1 CIRCUIT1 EDGE DETECT ICAP2 CIRCUIT2 OCMP1 LATCH1 LATCH2 OCMP2 PWM ...
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... L9805 16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MSB At t0 LSB is buffered Other instructions Returns the buffered Read LSB LSB value at t0 Sequence completed The user must read the MSB first, then the LSB value is buffered automatically ...
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... TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 19. Counter Timing Diagram, internal clock divided by 8 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF FFFD FFFE FFFF 0000 0001 FFFC FFFD 0000 FFFC FFFD L9805 0002 0003 0001 0000 35/103 ...
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... L9805 16-BIT TIMER (Cont’d) 5.2.3.3 Input Capture In this section, the index may The two input capture 16-bit registers (ICR1 and ICR2) are used to latch the value of the free run- ning counter after a transition detected by the ICAP i pin (see figure 5). ...
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... Figure 21. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ctive edge is rising edge. Note: A EDGE DETECT ICIE CIRCUIT1 ICR1 ICF1 FF02 L9805 CR1 (Control Register 1) IEDG1 SR (Status Register) ICF2 CR2 (Control Register 2) CC0 IEDG2 CC1 ...
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... L9805 16-BIT TIMER (Cont’d) 5.2.3.4 Output Compare In this section, the index may This function can be used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the Output Com- pare register and the free running counter, the out- put compare function: – ...
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... OCFi AND OCMPi PIN (OLVLi=1) OC1E OC2E CC1 CC0 (Control Register 2) (Control Register 1) OCIE OLVL2 OCF1 OCF2 0 (Status Register) FFFC FFFD FFFD FFFE FFFF 0000 COUNTER writes CPU FFFF L9805 CR2 CR1 Latch OLVL1 OCMP1 1 Latch OCMP2 FFFF 39/103 ...
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... L9805 16-BIT TIMER (Cont’d) 5.2.3.5 Forced Compare Mode In this section i may represent The main purpose of the Forced Compare mode is to easily generate a fixed frequency. The following bits of the CR1 register are used: FOLV FOLV 2 1 When the FOLV i bit is set, the OLVL i bit is copied to the OCMP i pin ...
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... The Input Capture interrupt is available. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one L9805 Pulse Width Modulation cycle OCMP1 = OLVL1 OCMP1 = OLVL2 Counter is reset to FFFCh ...
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... L9805 Figure 25. Pulse Width Modulation Mode Timing 34E2 FFFC FFFD FFFE COUNTER OCMP1 compare2 Note: OCR1=2ED0h, OCR2=34E2, OLVL1=0, OLVL2= 1 42/103 2ED0 2ED1 2ED2 OLVL2 OLVL1 compare1 34E2 FFFC OLVL2 compare2 ...
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... ICAP1 pin will trigger the capture falling edge triggers the capture rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin when- ever a successful comparison occurs with the OCR1 register. L9805 43/103 ...
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... L9805 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Timer1 Register Address: 0031h Timer2 Register Address: 0041h Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Enable. 0: Output Compare 1 function is enabled, but the OCMP1 pin is a general I/O ...
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... Bit 3 = OCF2 Output Compare Flag match (reset value) 1: The content of the free running counter has matched the content of the OCR2 register. To clear this bit, first read the SR register, then read or write the low byte of the OCR2 (OCLR2) reg- ister. Bit 2-0 = Unused. L9805 45/103 ...
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... L9805 16-BIT TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (ICHR1) Timer1 Register Address: 0034h Timer2 Register Address: 0044h Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). ...
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... INPUT CAPTURE 2 LOW REGISTER (ICLR2) 0 Timer1 Register Address: 003Dh Timer2 Register Address: 004Dh LSB Read Only Reset Value: Undefined This is an 8-bit read only register that contains the REGISTER low part of the counter value (transferred by the In- put Capture 2 event). 7 MSB L9805 0 LSB 0 LSB 0 LSB 47/103 ...
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... L9805 16-BIT TIMER (Cont’d) Table 8. 16-Bit Timer Register Map and Reset Values Address Register 7 Name (Hex.) Timer1: 32 CR1 ICIE Timer2: 42 Reset Value 0 Timer1: 31 CR2 OC1E Timer2: 41 Reset Value 0 SR Timer1: 33 ICF1 Timer2: 43 Reset Value 0 Timer1: 34 ICHR1 MSB - Timer2: 44 Reset Value ...
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... DUTYREG register, and when a match occurs the output level is reset. Figure 26. PWM Cycle When Counter = DUTYREG When Counter = CYREG Note: If the CYREG value is minor or equal than DUTYREG value, PWM output remains set. With a L9805 Pulse Width Modulation cycle OUT PWM = 0 OUT PWM = 1 Counter is reset 49/103 ...
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... L9805 DUTYREG value of 0000h, the PWM output is per- manently at low level, no matter of the value of CYREG. With a DUTYREG value of FFFFh, the PWM output is permanently at high level. Interrupt Request The EN_INT bit in CONREG register must be set to enable the interrupt generation. When the 16 Figure 27. PWM Generation ...
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... PS1 PS0 LSB Bit not used. L9805 0 LSB EN_ EN_ PS1 PS0 INT PWM PWM internal clock f CPU CPU CPU CPU CPU ...
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... L9805 PWM COUNTER REGISTER LOW (CTL) PWM1 Register Address: 0016h PWM2 Register Address: 001Eh Read Only Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the PWM counter value. 7 MSB Table 9. PWM Timing (f CPU Prescaler (PS) ...
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... Figure 28. PWM Block Diagram conreg | . | . | . | ps1 | ps2 | ps3 | en_int | en_pwm | clock 1 data bus dutyreg 16 2 COMPARATOR1 COMPARATOR2 M U 16-bit X counter L9805 cyreg 16 PWM logic IRQ 53/103 ...
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... Voltage thresholds are referred to the battery volt- age connected to VBR pin. This pin must be used as reference for the K bus. Voltage drops between this pin and the battery line can cause thresholds mismatch between the L9805 ISO trasceiver and the counterpart trasceiver(s) connected to the same bus line. See ...
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... Open Bus condition (external pull up missing). Figure 31. PWMI function PORT PA(7) PA7 PB(2) PWM PWMI I/O If the battery or ground connection are lost, the PWMI line shows a controlled impedance charac- teristic (see Sec- Figure PA(7) ALTERNATE INPUT PWM INPUT 1 PIEN DCSR L9805 Figure 30).. TIMER 2 ICAP2 55/103 ...
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... L9805 5.5 10-BIT A/D CONVERTER (AD10) 5.5.1 Introduction The Analog to Digital converter is a single 10-bit successive approximation converter with 4 input channels. Analog voltage from external sources are input to the converter through AD2,AD3 and AD4 pins. Channel 1 (AD1) is connected to the in- ternal temperature sensor (see Section Note The anti aliasing filtering must be accom- plished using an external RC filter ...
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... After trim- ming, being T specified precision can be achieved in the range T -80, max[T TRIM lated to the read temperature in Kelvin. 473 L9805 the trimming temperature, the TRIM +80, 150 C]. Precision is re- TRIM 57/103 ...
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... L9805 5.5.7 Register Description CONTROL/STATUS REGISTER (ADCCSR) Address: 0072h — Read/Write Reset Value: 0010 0000 (20h) 7 COCO ADIE 0 ADST 0 0 Bit 7,6 = Reserved Bit 5 =COCO (Read Only) Conversion Complete COCO is set (by the ADC) as soon as a conver- sion is completed (results can be read). COCO is cleared by setting ADST=1 (start of new conver- sion) ...
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... The same applies to overload frames which are recognized but never initiated. ST7 Internal Bus ST7 Interface TX/RX ID Buffer 3 Filter 0 Filter 1 10 Bytes 4 Bytes 4 Bytes SHREG EML CRC CAN 2.0B passive Core L9805 PSR ID BRPR BTR ICR ISR CSR TECR RECR 59/103 ...
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... L9805 CONTROLLER AREA NETWORK (Cont’d) 5.6.2 Main Features – Support of CAN specification 2.0A and 2.0B pas- sive – Three prioritized 10-byte Transmit/Receive mes- sage buffers – Two programmable global 12-bit message ac- ceptance filters – Programmable baud rates MBit/s – Buffer flip-flopping capability in transmission – ...
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... CRC Field 6 16 DLC CRC Inter-Frame Space or Overload Frame Error Delimiter 8 Data Frame or Remote Frame Bus Idle Inter-Frame Space or Error Frame 8 L9805 Inter-Frame Space or Overload Frame Ack Field CRC EOF Inter-Frame Space or Overload Frame Ack Field End Of Frame 2 7 Notes: • ...
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... L9805 CONTROLLER AREA NETWORK (Cont’d) 5.6.3.3 Modes of Operation The CAN Core unit assumes one of the seven states described below: – STANDBY. Stand-by mode is entered either on a chip reset or on resetting the RUN bit in the Control/Status Register (CSR). Any on-going transmission or reception operation is not inter- ...
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... RXIE bit in the ISR register is set three messages can be automatically received without intervention from the CPU because each buffer has its own set of status bits, greatly reducing the reactiveness require- ments in the processing of the receive inter- rupts. L9805 63/103 ...
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... L9805 – ERROR. The error management as described in the CAN protocol is completely handled by hard- ware using 2 error counters which get increment decremented according to the error condition. Both of them may be read by the appli- Figure 37. CAN Error State Diagram ERROR ACTIVE When 128 * 11 recessive bits occur: ...
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... RJW so that the transmit point is moved earlier safeguard against programming errors, the configuration of the Bit Timing Register (BTR) is only possible while the device is in STANDBY mode. NOMINAL BIT TIME BIT SEGMENT 2 (BS2) t BS1 SAMPLE POINT L9805 t BS2 TRANSMIT POINT 65/103 ...
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... L9805 CONTROLLER AREA NETWORK (Cont’d) 5.6.4 Register Description The CAN registers are organized as 6 general pur- pose registers plus 5 pages of 16 registers span- ning the same address space and primarily used for message and filter storage. The page actually selected is defined by the content of the Page Se- lection Register ...
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... Cleared by software to disable transmit error inter- rupts. Bit 0 = ETX Early Transmit Interrupt Read/Set/Clear Set by software to request the transmit interrupt to occur as soon as the arbitration phase has been passed successfully. Cleared by software to request the transmit inter- rupt to occur at the completion of the transfer. L9805 67/103 ...
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... L9805 CONTROLLER AREA NETWORK (Cont’d) CONTROL/STATUS REGISTER (CSR) Address: 005Ch - Read/Write Reset Value: 00h 7 0 BOFF EPSV SRTE NRTX FSYN WKPS Bit 6 = BOFF Bus-Off State Read Only Set by hardware to indicate that the node is in bus- off state, i.e. the Transmit Error Counter exceeds 255 ...
Page 69
... Address: 005Fh - Read/Write Reset Value: 00h PAGE[2:0] determine which buffer or filter page is mapped at addresses 0060h to 006Fh. PAGE2 + L9805 BS21 BS20 BS13 BS12 BS11 BS10 PAGE2 PAGE1 PAGE0 PAGE1 PAGE0 Page Title 0 0 Diagnosis 0 1 Buffer 1 ...
Page 70
... L9805 CONTROLLER AREA NETWORK (Cont’d) 5.6.4.2 Paged Registers LAST IDENTIFIER HIGH REGISTER (LIDHR) Read/Write Reset Value: Undefined 7 LID10 LID9 LID8 LID7 LID6 LID[10:3] are the most significant 8 bits of the last Identifier read on the CAN bus. LAST IDENTIFIER LOW REGISTER (LIDLR) Read/Write ...
Page 71
... Left untouched otherwise. Note that in order to prevent any message corrup- tion or loss of context, LOCK cannot be set nor re- 0 set while BUSY is set. Trying will result in LOCK not changing state. RDY BUSY LOCK L9805 71/103 ...
Page 72
... L9805 CONTROLLER AREA NETWORK (Cont’d) FILTER HIGH REGISTERS (FHRx) Read/Write Reset Value: Undefined 7 FIL11 FIL10 FIL9 FIL8 FIL7 FIL[11:3] are the most significant 8 bits of a 12-bit message filter. The acceptance filter is compared bit by bit with the identifier and the RTR bit of the incoming message ...
Page 73
... Paged Reg11 Paged Reg12 Paged Reg13 Paged Reg12 Paged Reg13 Paged Reg12 Paged Reg13 Paged Reg14 Paged Reg13 Paged Reg14 Paged Reg13 Paged Reg14 Paged Reg15 6Fh Paged Reg14 Paged Reg15 Paged Reg14 Paged Reg15 Paged Reg15 Paged Reg15 L9805 73/103 ...
Page 74
... L9805 CONTROLLER AREA NETWORK (Cont’d) Figure 39. Page Maps PAGE 0 PAGE 1 60h LIDHR 61h LIDLR 62h DATA01 63h DATA11 64h DATA21 65h DATA31 66h DATA41 67h DATA51 Reserved 68h DATA61 69h DATA71 6Ah 6Bh Reserved 6Ch 6Dh 6Eh TECR 6Fh RECR ...
Page 75
... MSK0 TEC7 TEC6 TEC5 TEC4 REC7 REC6 REC5 REC4 L9805 SCIF ORIF TEIF EPND SCIE ORIE TEIE ETX NRTX FSYN WKPS RUN BRP3 ...
Page 76
... CAN at all or using it for particular func- ) from tions (such like debugging). Current consumption COM reduction, when disabling the trasceiver, can be as high as 15mA. Note When the CAN capabilities of L9805 are not needed additional consumption reduction can be achieved putting the CAN controller in Stand-by Mode (see Section OVERCURRENT ...
Page 77
... VBL VBR OUTL OUTR PGND PGND the outputs OUTL and OUTR are in high imped- ance state. Being '0' the status after reset of EN, the bridge is in safe condition (OUTL=OUTR=Z). Therefore the L9805 SC_UR OVT UR DR OVT SC_DR 77/103 ...
Page 78
... L9805 safe condition is guaranteed in undervoltage con- dition (LVD reset) and in case of main clock (Safe- guard reset) or software (Watchdog reset) failures. Each power DMOS has its own over current detec- tor circuit generating SC_xx signals (see 41). SC_xx signals are ORed together to generate SC flag in BCSR register ...
Page 79
... L9805 Operation Configuration INHIBIT Full or BRAKE Two Half Bridges Full or BACK Two Half Bridges Full or FORWARD Two Half Bridges Full or BRAKE Two Half Bridges BRAKE Full Bridge FORWARD Full Bridge ...
Page 80
... L9805 Drive EN PWM_EN DIR PWM1 IN1 IN2 Note The DIR signal is internally synchronized with the PWM1 and PWM2 signals according to the selected Driving Mode. After writing the DIR bit in BCSR register, the direction changes in corre- spondence with the first rising edge of PWM1 ...
Page 81
... DIR bit can not be latched and the driv- ing direction does not change even changing DIR bit in BCSR. Bit 5= SC: Short Circuit flag (read only) selection bit if Bit 6= OVT: Overtemperature flag (read only) Bit 7= PIE: Power section interrupt enable. L9805 driving mode selection bit IN1 IN2 Driving Mode X ...
Page 82
... L9805 5.9 EEPROM (EEP) 5.9.1 Introduction The Electrically Erasable Programmable Read Only Memory is used to store data that need a non volatile back-up. The use of the EEPROM requires a basic protocol described in this chapter. Software or hardware reset and halt modes are managed immediately, stopping the action in progress ...
Page 83
... The EEPROM enters the halt mode if the micro- controller did execute the halt instruction. The EEPROM will stop the function in progress, and will enter in this low consumption mode. Erase cycle Write cycle Tprog L9805 Read operation allowed Interrupt vector fetch 83/103 ...
Page 84
... L9805 Figure 45. EEPROM Programming Flowchart Write bytes in the same row (with the same 12 Most Significant Bits of the address) 5.9.3 Register Description EEPROM CONTROL REGISTER (EECR) Address: 002Ch - Read/Write Reset Value: 0000 0000 (00h E2ITE Bit 7:3 = Reserved, forced by hardware to 0. ...
Page 85
... Special management of wrong EEPROM access read happens while E2LAT=1, then the data bus will not be driven write access happens while E2LAT=0, then the data on the bus will not be latched. The data latches are cleared when the user sets E2LAT bit. L9805 85/103 ...
Page 86
... L9805 6 INSTRUCTION SET 6.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5 The ST7 Instruction set is designed to minimize the number of bytes required per instruction Table 13 ...
Page 87
... Direct (short): The address is a byte, thus requires only one byte after the opcode, but only allows address- ing space. Direct (long): The address is a word, thus allowing 64Kb ad- dressing space, but requires 2 bytes after the op- code. L9805 87/103 ...
Page 88
... L9805 INSTRUCTION SET OVERVIEW (Cont’d) Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register ( with an offset which follows the opcode. No Offset, Long and Short Indexed Function Instruction LD Load ...
Page 89
... Available Relative Direct/Indirect Function Instructions JRxx Conditional Jump CALLR Call Relative The relative addressing mode consists of two sub- modes: Relative (direct): The offset is following the opcode. Relative (indirect): The offset is defined in memory, which address follows the opcode. L9805 89/103 ...
Page 90
... L9805 INSTRUCTION SET OVERVIEW (Cont’d) 6.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations ...
Page 91
... M dec Y reg, M Pop CC inc X reg [TBL.w] jrf * (no Port A Interrupts) (Port A interrupt Unsigned < Jmp if unsigned >= Unsigned > L9805 ...
Page 92
... L9805 INSTRUCTION SET OVERVIEW (Cont’d) JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry flag RET Subroutine Return RIM Enable Interrupts RLC ...
Page 93
... GND All the voltage in the following tables are refer- enced to GND. Value -65 to +150 150 2000 GND - 0 0.3 DD GND - GND - -25.....+25 L9805 0.3V Unit V mV °C ° 93/103 ...
Page 94
... L9805 7.2 POWER CONSIDERATIONS The average chip-junction temperature, T grees Celsius, may be calculated using the follow- ing equation (1 Where: – the Ambient Temperature – is the Package Junction-to-Ambient Thermal JA Resistance, in C/W, – the sum of P and INT I/O – ...
Page 95
... Figure 47. Hiquad-64: Thermal impedance Zth (ºC/ Multilayer optimised PCB Dissipated power (W) 2s1p 1Oz PCB Die size 6x6 mm² Power amb. 22 ºC Natural convection 1 10 Time (s) L9805 Die size 6x6 mm² T amb. 22 ºC Natural convection 7 6 100 1,000 95/103 ...
Page 96
... L9805 7.3 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. MAX 0.25 A2 2.50 2. 0.10 b 0.22 0.38 c 0.23 0.32 D 17.00 17.40 D1 (1) 13.90 14.00 14.10 D2 2.65 2.80 2.95 E 17.00 17.40 E1 (1) 13.90 14.00 14.10 e 0.65 E2 2.35 2.65 E3 9.30 9.50 9.70 E4 13.30 13.50 13.70 F 0.10 G 0.12 L 0.80 1. (max.) S (min.), 7˚(max.) (1): "D1" and "E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm(0.006inch) per side ...
Page 97
... ADC input filtering VB1 PGND VB2 PGND VDD PGND VCC PGND AGND AGND GND CAN_H CAN_L VB PWMO PWMI PB[7:0],PA[1:0] VPP/TM 1M** GND GND L9805 VBL VBL VBL VBR VBR VBR PGND OUTL OUTL OUTL * MOTOR OUTR OUTR OUTR AD2 *** AD3 *** AD4 *** ...
Page 98
... L9805 7.5 DC ELECTRICAL CHARACTERISTICS (T = -40 to +150°C, VB=12V unless otherwise specified) J GENERAL Symbol Parameter VB1 Supply Voltage VBR, VBL Power Supply Voltage = VB I1 Supply Current from VB1 I Input Current IN Note 1. Halt mode is not allowed if Watchdog or Safeguard are enabled Note 2. A current of 5mA can be forced on each pin of the digital section without affecting the functional behaviour of the device. ...
Page 99
... Min. I=-5mA - I=-1.6mA - I=5mA 3.1 I=1.6mA 3.4 GND<V <V -10 PIN DD V =GND =50pF - l C =50pF - l Value Conditions Min 1.5 4096 12,288 MHz 1.54 cpu L9805 Typ Max Unit - 1 0 250 Unit Typ. Max 16 MHz 8 MHz t CPU t CPU 500 ...
Page 100
... L9805 7.7 OPERATING BLOCK ELECTRICAL CHARACTERISTICS These device-specific values take precedence over any generic values given elsewhere in the document -40... +150 GND = 5 V unless otherwise specified A/D Converter Symbol Parameter V Resolution AL AE Absolute Error FSC Full Scale Error ZOE Zero Offset Error ...
Page 101
... TX = Low Level; VDD = Low Level; VDD = -2V High CANL Level V = 6.5V High CANH ) Level V = -2V High CANL Level V = 6.1V High CANH ) Level = DIFF L9805 Typ Max Unit 100 mA Typ Max Unit -1 0.45*VB VB 0.025*VB 0.8 0.5 8 Typ Max Unit 0.6 1.1 1.7 ...
Page 102
... L9805 CAN TRANSCEIVER Ohm, see note 1, unless otherwise specified. Symbol Parameter Delay Time from V DIFF DIFF CANH CANL Disabled Transmission Time for t D Overcurrent Protection VCANH Slew Rate Between 20 and 80% VCANL Slew Rate Between 20 and 80% ...
Page 103
... STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com L9805 103/103 ...