MACH4-96-96-15 Lattice Semiconductor Corp., MACH4-96-96-15 Datasheet - Page 12

• Manufacturer Part Number: MACH4-96-96-15
• Description: High-performance Ee Cmos Programmable Logic
• Manufacturer: Lattice Semiconductor Corp.

SpeedLocking for Guaranteed Fixed Timing
The MACH 4 architecture allows allocation of up to 20 product terms to an individual macrocell
with the assistance of an XOR gate without incurring additional timing delays. Using this
architectural strength, the M4-96/96 provides the industry’s highest-speed and only fixed timing
at 5-V supply voltages. This SpeedLocking feature delivers guaranteed fixed speed independent
of logic path, routing resources, or design refits.
5-V In-System Programming
Another benefit of the JTAG circuitry is the ability to use the JTAG port for 5-V programming.
This allows the device to be soldered to the board before programming. Once the device is
attached, the delicate Plastic Quad Flat Pack, or PQFP, leads are protected from programming
and testing operations that could potentially damage them. Programming and verification of the
device is done serially which is ideal for on-board programming since it only requires the use
of the Test Access Port. There is an optional ENABLE pin which can be used to inhibit
programming for additional security. These devices can be programmed in any JTAG chain.
JTAG Boundary Scan Testing
JTAG is the commonly used acronym for the IEEE Standard 1149.1-1990. The JTAG standard
defines input and output pins, logic control functions, and instructions. Vantis has incorporated
this standard into the M4-96/96 device.
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V A N T I S
Output Enable
Product Term
Switch Matrix
From Output
To Input
Individual
Switch
Matrix
Figure 6. I/O Cell
MACH4-96/96-15
Q
D/L*
Block CLK0
Block CLK1
Block CLK2
Block CLK3
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