NSBMC096-16 National Semiconductor Corporation, NSBMC096-16 Datasheet - Page 10

• Manufacturer Part Number: NSBMC096-16
• Description: Nsbmc096-16/-25/-33 Burst Memory Controller
• Manufacturer: National Semiconductor Corporation

Application Example
System Clock
Refresh Rate
Memory Size
Buffer Mode
Interleave
Row Address Hold
Required Configuration for startup
Configuration Setup
The ease with which the NSBMC096 may be integrated into
a system design is illustrated in the diagram in Figure 4 The
system shown supports an i960 CA CF with between 2 and
128 MB of memory depending on the devices selected
managed by a single NSBMC096 This specific example ac-
commodates 1 MB x 1 4 MB x 1 or 16 MB x 1 devices
Connection of the NSBMC096 to the i960 CA CF processor
is accomplished simply by wiring together pins with the
same names The only exceptions are READY and BTERM
If the NSBMC096 is the only device that generates these
two signals they can be connected directly to the appropri-
0xFF0F0000 (0xFF0F0000 0)
0xFF0F0658 (0xFF0F0400
0xFF0F0A20 (0xFF0F0800
0xFF0F0C00 (0xFF0F0C00 0)
25 MHz
16 ms per row (0
1 MB x 1 (Size
Signal 1
(Mode 1)
Enabled
(Row Address Hold
clock cycle
0000 0000 1000 1000 1001 0110 0000 0000 (0x00889600)
a
a
e
FIGURE 4 Possible System Interconnection using V96BMC
(0x96 m 2) 0)
(0x88 m 2) 0)
CEA Signal 2
(Mode 1 where TXA is used as CEA and TXB as CEB)
e
c
1)
18)
e
0)
e
CEB
Config bits 7 0
Config bits 31 24
Config bits 15 8
Config bits 23 16
10
Cycle Extend
Burst Write
Base Address
ate inputs of the processor and require only a small pull up
resistor to keep them de-asserted when in the high imped-
ance state
If multiple processor peripherals are connected to READY
or BTERM 3-state drivers should be used in such a manner
that the signals are actively de-asserted prior to the driver
being placed in its’ high impedance state If this rule is fol-
lowed a simple ‘‘wire or’’ can be used Alternately all
sources of READY or BTERM can be combined using multi-
ple input gates and the processor signals driven by the out-
puts
e
e
e
0
e
0
0
0
Disabled (3 clock RAS derived from
t
of DRAM buffer delay of 74FCT245
and setup time of the processor’s data
inputs)
Disabled
8 MB (0b000000000100)
RSHL
of NSBMC096 RAS access time
TL V 11805 – 7