NSBMC096-16 National Semiconductor Corporation, NSBMC096-16 Datasheet

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NSBMC096-16

Manufacturer Part Number
NSBMC096-16
Description
Nsbmc096-16/-25/-33 Burst Memory Controller
Manufacturer
National Semiconductor Corporation
Datasheet
C 1995 National Semiconductor Corporation
NSBMC096-16 -25 -33 Burst Memory Controller
General Description
The NSBMC096 Burst Memory Controller is an integrated
circuit which implements all aspects of DRAM control for
high performance systems using an i960
SuperScalar Embedded Processor The NSBMC096 is func-
tionally equivalent to the V96BMC
The extremely high instruction rate achieved by these proc-
essors place extraordinary demands on memory system de-
sign if maximum throughput is to be sustained and costs
minimized
Static RAM offers a simple solution for high speed memory
systems However high cost and low density make this an
expensive and space consumptive choice
Dynamic RAMs are an attractive alternative with higher den-
sity and low cost Their drawbacks are slower access time
and more complex control circuitry required to operate
them
The access time problem is solved if DRAMs are used in
page mode In this mode access times rival that of static
RAM The control circuit problem is resolved by the
NSBMC096
The function that the NSBMC096 performs is to optimally
translate the burst access protocol of the i960 CA CF to the
page mode access protocol supported by dynamic RAMs
The device manages one or two-way interleaved arrange-
ments of DRAMs such that during burst access data can be
read or written at the rate of one word per system clock
cycle
Block Diagram
This document contains information concerning a product that has been developed by National Semiconductor Corporation V3 Corporation This information
is intended to help in evaluating this product National Semiconductor Corporation V3 Corporation reserves the right to change and improve the specifications
of this product without notice
TRI-STATE is a registered trademark of National Semiconductor Corporation
NSBMC096
i960 is a registered trademark of Intel Corporation
V96BMC
TM
TM
is a trademark of V3 Corporation
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation
TL V 11805
TM
CA CF
The NSBMC096 has been designed to allow maximum flexi-
bility in its application The full range of processor speeds is
supported for a wide range of DRAM speeds sizes and or-
ganizations
No glue logic is required because the bus interface is cus-
tomized to the i960 CA CF System integration is further
enhanced by providing a 24-bit heartbeat timer and a bus
watch timer on-chip
The NSBMC096 is packaged as a 132-pin PQFP with a foot-
print of only 1 3 square inches It reduces design complexi-
ty space requirements and is fully derated for loading tem-
perature and voltage
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Interfaces directly to the i960 CA
Integrated Page Cache Management
Manages Page Mode Dynamic Memory devices
On-chip Memory Address Multiplexer Drivers
Supports DRAMs trom 256 kB to 64 MB
Bit counter timer
Non-interleaved or two way interleaved operation
5-Bit Bus Watch Timer
Software-configured operational parameters
High-Speed Low Power CMOS technology
TL V 11805 – 1
RRD-B30M115 Printed in U S A
August 1993

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NSBMC096-16 Summary of contents

Page 1

... NSBMC096-16 -25 -33 Burst Memory Controller General Description The NSBMC096 Burst Memory Controller is an integrated circuit which implements all aspects of DRAM control for high performance systems using an i960 SuperScalar Embedded Processor The NSBMC096 is func- tionally equivalent to the V96BMC TM The extremely high instruction rate achieved by these proc- ...

Page 2

... Logic and Connection Diagrams TL V 11805 – 2 Order Number NSBMC096VF See Package Number VF132A 11805 – 3 ...

Page 3

Pin Descriptions Pin Signal Name 1 A14 2 A15 3 A16 A17 6 A19 7 A20 8 A18 9 A21 10 A24 11 A22 12 A23 13 A26 14 A25 15 A27 19 A31 20 A28 ...

Page 4

Pin Descriptions (Continued) i960 CA CF INTERFACE The following pins are functionally equivalent to those on the i960 CA CF from which their names are taken Like named pins on the i960 CA CF and the NSBMC960 are to Pin ...

Page 5

Pin Descriptions (Continued) MEMORY INTERFACE The NSBMC960 is designed to drive a memory array orga- nized as 2 leaves each of 32 bits The address and control signals for the memory array are output through high current Pin A(A B)0 ...

Page 6

Functional Description PRODUCT OVERVIEW The NSBMC960 couples the i960 CA CF interface to DRAM access protocols generates bus buffer and data multiplexor controls and incorporates system and bus moni- tor timing resources These functional elements are shown in Figure 1 ...

Page 7

... Functional Description (Continued) BLOCK ADDRESS FIELD Once configured a NSBMC096 responds to access re- quests within the programmed block address range The programmed value sets the starting address of the block while the size of the block is determined by the DRAM size FIGURE 3 Configuration Register Control Fields ...

Page 8

... Access made to a region configured for external ready can hang the processor if for some reason READY is not returned to ter- minate the access The NSBMC096 can detect such a con- dition and if the bus watch feature is enabled will return READY and BERR ...

Page 9

... The third field is the Iow two bits of the refresh rate The NSBMC096 has been designed such that if any of the bits in the operation control field is written with a ‘‘1’’ ac- ...

Page 10

... Connection of the NSBMC096 to the i960 CA CF processor is accomplished simply by wiring together pins with the same names The only exceptions are READY and BTERM If the NSBMC096 is the only device that generates these two signals they can be connected directly to the appropri- FIGURE 4 Possible System Interconnection using V96BMC ...

Page 11

... ARA lay) Two simple access cycles are shown in the diagram The first is a read cycle that assumes that the NSBMC096 was idle prior to the start of the cycle the second is backed onto the first to show the effect of RAS pre-charge imposed ...

Page 12

Timing Parameters (Continued) FIGURE 6 Basic Access Timing FIGURE 7 Burst Access Timing 11805 – 11805 – 10 ...

Page 13

Timing Parameters (Continued) FIGURE 8 Burst Access w t PCache Hit Figures 8 and 9 show the sequence of events that can oc- cur when PCache is enabled The sequence in Figure 8 shows two back-to-back bursts in the same ...

Page 14

Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Input ...

Page 15

AC Timing Parameters (Unless otherwise stated V Symbol Description 1 t Address Strobe Setup Time ADSU 2 t Address Strobe Hold Time ADH 3 t Synchronous Input Setup Synchronous Input Hold BLAST Input Setup ...

Page 16

... Intel i960 ERRATUM 2 When the NSBMC096 is programmed for extended timing mode operation back to back memory read cycles will fail RECOMMENDED FIX Program the i960CA CF memory region for the NSBMC096 to insert one wait state following each memory access ( Set N 1) XDA ...

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17 ...

Page 18

... Italiano National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Order Number NSBMC096VF NS Package Number VF132A 2 A critical component is any component of a life ...

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