MT9HTF12872RHY-53E Micron Semiconductor Products, MT9HTF12872RHY-53E Datasheet - Page 6

• Manufacturer Part Number: MT9HTF12872RHY-53E
• Description: 512mb, 1gb X72, Ecc, Sr 200-pin Ddr2 Sdram Sordimm
• Manufacturer: Micron Semiconductor Products

General Description
Register and PLL Operation
Temperature Sensor
Serial Presence-Detect Operation
PDF: 09005aef828742dd/Source: 09005aef82874316
HTF9C64_128x72RH.fm - Rev. B 10/07 EN
The MT9HTF6472RH and MT9HTF12872RH DDR2 SDRAM modules are high-speed,
CMOS, dynamic random access 512MB and 1GB memory modules organized in a x72
configuration. These modules use a 512Mb DDR2 SDRAM device with four internal
banks or a 1Gb DDR2 SDRAM device with eight internal banks.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
These DDR2 SDRAM modules operate in registered mode, where the command/address
input signals are latched in the registers on the rising clock edge and sent to the DDR2
SDRAM devices on the following rising clock edge (data access is delayed by one clock
cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock
signals (CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address,
command, control, and clock signal loading by isolating DRAM from the system
controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the
JEDEC clock reference board. Registered mode will add one clock cycle to CL.
An on-board temperature sensor provides the ability to monitor the module tempera-
ture along with monitoring alarms. Programmable registers can be used to specify
temperature events and critical boundaries. The EVENT# pin is used to signal when
different conditions occur based on how the registers are defined.
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (1:0), which
provide four unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
module, permanently disabling hardware write protect.
512MB, 1GB (x72, ECC, SR) 200-Pin DDR2 SDRAM SORDIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2007 Micron Technology, Inc. All rights reserved.
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