KSZ8862 Micrel Semiconductor, KSZ8862 Datasheet - Page 59

• Manufacturer Part Number: KSZ8862
• Description: 2-port Ethernet Switch With Non-pci Interface And Fiber Support
• Manufacturer: Micrel Semiconductor

Bank 2 Host MAC Address Register Middle (0x02): MARM
The middle word of Host MAC address.
The following table shows the register bit fields:
Bank 2 Host MAC Address Register High (0x04): MARH
The high word of Host MAC address.
The following table shows the register bit fields.
Bank 3 On-Chip Bus Control Register (0x00): OBCR
This register controls the on-chip bus speed for the KSZ8862M. It is used for power management when the external host
CPU is running at a slow frequency. The default of the on-chip bus speed is 125 MHz without EEPROM. When the
external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance.
Micrel, Inc.
April 2007
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-2
1-0
Default Value
-
Default Value
-
Default Value
-
Default Value
-
0x0
R/W
RW
R/W
RW
R/W
RW
R/W
RO
RW
Description
MARL MAC Address Low
The least significant word of the MAC address.
Description
MARM MAC Address Middle
The middle word of the MAC address.
Description
MARH MAC Address High
The Most significant word of the MAC address.
Description
Reserved
OBSC On-Chip Bus Speed Control
00: 125MHz.
01: 62.5MHz.
10: 41.66MHz.
11: 25MHz.
Note: When external EEPROM is enabled, the bit 1 in Configparm word (0x6H) is used to
contol this speed as below:
Bit 1 = 0 , this value will be 00 for 125 MHz.
Bit 1 = 1 , this value will be 11 for 25 MHz.
(User still can write these two bits to change speed after EEPROM data loaded)
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KSZ8862-16/32MQL
M9999-040407-3.0