STMPE1601 STMicroelectronics, STMPE1601 Datasheet - Page 28

• Manufacturer Part Number: STMPE1601
• Description: 16-bit Enhanced Port Expander With Keypad And Pwm Controller Xpander Logic
• Manufacturer: STMicroelectronics

Interrupt system
INT_EN_GPIO_MASK
Address:
Type:
Reset:
Description:
INT_STA_GPIO
Address:
Type:
Reset:
Description:
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IEG15
ISG15
RW
RW
15
15
0
0
IEG14
ISG14
RW
RW
14
14
0
0
[15:0] IEG[x]: interrupt enable GPIO mask (where x = 15 to 0)
[15:0] ISG[x]
IEG13
ISG13
RW
RW
13
13
0
0
INT_EN_GPIO_MASK_msb
0x16, 0x17
R/W
0x00
The interrupt enable GPIO mask register is used to enable the interruption from a
particular GPIO interrupt source to the host. The IEG[15:0] bits are the interrupt
enable mask bits correspond to the GPIO[15:0] pins
.
Writing a ‘1’ to the IE[x] bit will enable the interruption to the host.
0x18, 0x19
R/W
0x00
The interrupt status GPIO register monitors the status of the interruption from a
particular GPIO pin interrupt source to the host. Regardless whether the
INT_EN_GPIO_MASK bits are enabled or not, the INT_STA_GPIO bits are still
updated. The INT_STA_G[15:0] bits are the interrupt status bits correspond to the
GPIO[15:0] pins.
Interrupt status GPIO (where x = 15 to 0)
Read:
Interrupt status of the GPIO[x].
Write:
A write to a ISG[x] bit with a value of ‘1’ will clear the interrupt and a write with a value of ‘0’ has
no effect on the ISG[x] bit.
INT_STA_GPIOR_msb
IEG12
ISG12
RW
RW
12
12
0
0
IEG11
ISG11
RW
RW
11
11
0
0
IEG10
ISG10
RW
Interrupt enable GPIO mask register
Interrupt status GPIO register
RW
10
10
0
0
IEG9
ISG9
RW
RW
9
0
9
0
IEG8
ISG8
RW
RW
8
0
8
0
IEG7
ISG7
RW
RW
7
0
7
0
IEG6
ISG6
RW
RW
6
0
6
0
IEG5
ISG5
RW
RW
5
INT_EN_GPIO_MASK _lsb
0
5
0
INT_STA_GPIOR _lsb
IEG4
ISG4
RW
RW
4
0
4
0
IEG3
ISG3
RW
RW
3
0
3
0
IEG2
ISG2
RW
RW
2
0
2
0
STMPE1601
IEG1
ISG1
RW
RW
1
0
1
0
IEG0
ISG0
RW
RW
0
0
0
0