LPC2460 NXP Semiconductors, LPC2460 Datasheet - Page 42

• Manufacturer Part Number: LPC2460
• Description: Flashless 16-bit/32-bit Micro; Ethernet, Can, Isp/iap, Usb 2.0 Device/host/otg, External Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2460_2
Preliminary data sheet
7.25.1 Reset
7.25.2 Boot process
7.25 System control
On the LPC2460, I/O pads are powered by the 3.3 V (V
V
the CPU and most of the peripherals.
Although both the I/O pad ring and the core require a 3.3 V supply, different powering
schemes can be used depending on the actual application requirements.
The first option assumes that power consumption is not a concern and the design ties the
V
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
a dedicated 3.3 V supply for the CPU (V
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
Reset has four sources on the LPC2460: the RESET pin, the Watchdog reset, power-on
reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input
pin. Assertion of chip Reset by any source, once the operating voltage attains a usable
level, starts the Wake-up timer (see description in
causing reset to remain asserted until the external Reset is de-asserted, the oscillator is
running, and a fixed number of clocks have passed.
Once the internal reset is removed, all of the processor and peripheral registers have
been initialized to predetermined values and the LPC2460 continues with booting from an
external static memory.
The processor always boots from the off-chip static memory bank 1, executing code from
address 0x8100 0000 (see
boot process initiated by POR, the boot pins P3[15]/D15 and P3[14]/D14 are sampled,
and the external memory banks 0 and 1 are configured with the same data bus width. The
data bus width is determined by the setting of the two boot pins. Unused address pins are
configured as GPIO. See
an example of address and data bus interfacing.
Remark: After POR, the address ranges of chip select 1 and chip select 0 are swapped.
The user code residing in the external boot memory must be linked to execute from
address location 0x8000 0000.
DD(DCDC)(3V3)
DD(3V3)
and V
pins power the on-chip DC-to-DC converter which in turn provides power to
DD(DCDC)(3V3)
Rev. 02 — 1 February 2008
Section 11.2 “Suggested boot memory interface solutions”
Table 5 “LPC2460 memory usage and
pins together. This approach requires only one 3.3 V power
DD(DCDC)(3V3)
Section 7.24.3 “Wake-up
). Having the on-chip DC-DC
DD(3V3)
) pins, while the
Fast communication chip
details”). During the
LPC2460
© NXP B.V. 2008. All rights reserved.
timer”),
DD(3V3)
42 of 68
) and
for