AT91SAM9M10 ATMEL Corporation, AT91SAM9M10 Datasheet - Page 28

• Manufacturer Part Number: AT91SAM9M10
• Description: At91 Arm Thumb-based Microcontrollers
• Manufacturer: ATMEL Corporation

7.3.2
7.3.3
28
AT91SAM9M10
External Bus Interface
DDR2/LPDDR Controller
Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Mini-
mizes Transaction Latency.
• Integrates Three External Memory Controllers:
• Additional logic for NAND Flash and CompactFlash
• Optional Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64MBytes linear per chip select)
• Up to 6 chip selects, Configurable Assignment:
• Supports AHB Transfers:
• Supports DDR-SDRAM 2, LPDDR
• Numerous Configurations Supported
• Programming Facilities
• Energy-saving Capabilities
• Power-up Initialization by Software
• CAS Latency of 2, 3 Supported
• Reset function supported (DDR2)
• Auto Precharge Command Not Used
• On Die Termination not supported
• OCD mode not supported
– Static Memory Controller
– DDR2/SDRAM Controller
– SLC Nand Flash ECC Controller
– Static Memory Controller on NCS0
– DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash
– Word, Half Word, Byte Access.
– 2K, 4K, 8K, 16K Row Address Memory Parts
– DDR2 with Four Internal Banks
– DDR2/LPDDR with 16-bit Data Path
– One Chip Select for DDR2/LPDDR Device (256 Mbytes Address Space)
– Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
– Automatic Update of DS, TCR and PASR Parameters
– Self-refresh, Power-down and Deep Power Modes Supported
Average Latency of Transactions)
TM
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6355AS–ATARM–06-Jan-10
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