AT91SAM9M10 ATMEL Corporation, AT91SAM9M10 Datasheet - Page 21

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AT91SAM9M10

Manufacturer Part Number
AT91SAM9M10
Description
At91 Arm Thumb-based Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet

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6.5
6355AS–ATARM–06-Jan-10
DMA Controller
Figure 6-2.
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals below. The hardware interface numbers are also given below in
Table
Table 6-7.
Instance Name
MCI0
SPI0
SPI0
SPI1
SPI1
SSC0
SSC0
SSC1
SSC1
AC97C
AC97C
MCI1
• Two Masters
• Embeds 8 channels
• 64 bytes/FIFO for Channel Buffering
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• memory to memory transfer
• Peripheral to memory
• Memory to peripheral
USB Selection
DMA Channel Definition
T/R
TX/RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX/RX
Transceiver
DMA Channel HW
interface Number
0
1
2
3
4
5
6
7
8
9
10
13
PA
HS
HS EHCI
FS OHCI
DMA
PB
0
Transceiver
HS
USB
DMA
HS
1
EN_UDPHS
AT91SAM9M10
21

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