WM8768 Wolfson Microelectronics plc, WM8768 Datasheet - Page 22

• Manufacturer Part Number: WM8768
• Description: 24-bit, 192khz 8-channel Dac
• Manufacturer: Wolfson Microelectronics plc

WM8768
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The IWL[1:0] bits are used to control the input word length.
Note: If 32-bit mode is selected in right justified mode, the WM8768 defaults to 24 bits.
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8768 pads the unused LSBs with zeros. If
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.
Note: In 24 bit I
minimum of 24 BCLKs and low for a minimum of 24 BCLKs. If exactly 32 bit clocks occur in one
left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode.
A number of options are available to control how data from the Digital Audio Interface is applied to
the DAC channels.
DAC OUTPUT PHASE
The DAC phase control word determines whether the output of each DAC is non-inverted or inverted
DIGITAL ZERO CROSS-DETECT
The digital volume control also incorporates a zero cross detect circuit which detects a transition
through the zero point before updating the digital volume control with the new volume. This is
enabled by control bit DZCEN.
By default, LRCLK and DIN1/2/3/4 are sampled on the rising edge of BCLK and should ideally
change on the falling edge. Data sources that change LRCLK and DIN1/2/3/4 on the rising edge of
BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK
to the inverse of that shown in Figure 13, Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18.
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
Interface Control
Interface Control
DAC4 Control
DAC Control
DAC Phase
0000011
0000011
0000011
0001001
0001111
2
S mode, any width of 24 bits or less is supported provided that LRCLK is high for a
BIT
BIT
5:4
BIT
BIT
8:6
3
0
3
DZCEN
LABEL
LABEL
LABEL
PHASE4
PHASE
LABEL
BCP
[1:0]
IWL
[2:0]
DEFAULT
DEFAULT
DEFAULT
DEFAULT
00
0
0
000
0
BCLK Polarity
Input Word Length
DAC Digital Volume Zero Cross
Enable:
Bit
0
1
2
N/A
0 : normal BCLK polarity
1: inverted BCLK polarity
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
0: Zero cross detect enabled
1: Zero cross detect disabled
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DAC
DAC1L/R
DAC2L/R
DAC3L/R
DAC4L/R
PD Rev 4.2 July 2005
Production Data
Phase
1 = invert
1 = invert
1 = invert
1 = invert
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