WM8522 Wolfson Microelectronics plc, WM8522 Datasheet - Page 21

• Manufacturer Part Number: WM8522
• Description: 24-bit, 192khz 6-channel Dac With 1.7vrms Line Driver
• Manufacturer: Wolfson Microelectronics plc

Production Data
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By default, LRCLK and DIN1/2/3 are sampled on the rising edge of BCLK and should ideally change
on the falling edge. Data sources that change LRCLK and DIN1/2/3 on the rising edge of BCLK can
be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the
inverse of that shown in Figure 13, Figure 14, Figure 15, Figure 16, and Figure 17.
The IWL[1:0] bits are used to control the input word length.
Note: 32-bit right justified mode is not supported.
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8522 pads the unused LSBs with zeros. If
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.
Note: In 24 bit I
minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
A number of options are available to control how data from the Digital Audio Interface is applied to
the DAC channels.
DAC OUTPUT PHASE
The DAC phase control word determines whether the output of each DAC is non-inverted or inverted
DIGITAL ZERO CROSS-DETECT
The digital volume control also incorporates a zero cross detect circuit which detects a transition
through the zero point before updating the digital volume control with the new volume. This is
enabled by control bit DZCEN.
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
Interface Control
Interface Control
DAC Control
DAC Phase
0000011
0000011
0000011
0001001
2
S mode, any width of 24 bits or less is supported provided that LRCLK is high for a
BIT
BIT
BIT
5:4
BIT
8:6
0
3
LABEL
PHASE
LABEL
LABEL
LABEL
ZCD
BCP
[1:0]
IWL
[2:0]
DEFAULT
DEFAULT
DEFAULT
DEFAULT
000
0
00
0
DAC Digital Volume Zero Cross
Enable:
BCLK Polarity (DSP Modes):
Input Word Length:
Bit
0
1
2
0: Normal BCLK polarity
1: Inverted BCLK polarity
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
0: Zero cross detect enabled
1: Zero cross detect disabled
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DAC
DAC1L/R
DAC2L/R
DAC3L/R
PD, Rev 4.1, July 2009
WM8522
Phase
1 = invert
1 = invert
1 = invert
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