LCMXO256 Lattice Semiconductor Corp., LCMXO256 Datasheet - Page 42

• Manufacturer Part Number: LCMXO256
• Description: Machxo Family Data Sheet
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
sysCLOCK PLL Timing
MachXO “C” Sleep Mode Timing
t
t
t
t
Rev. A 0.19
PWRDN
PWRUP
WSLEEPN
WAWAKE
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. CLKOS as compared to CLKOP output.
Rev. A 0.19
Symbol
IN
OUT
OUT2
VCO
PFD
DT
PH
OPJIT
SK
W
LOCK
PA
IPJIT
FBKDLY
HI
LO
RST
Parameter
4
2
1
SLEEPN
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width
SLEEPN Low to Power Down
SLEEPN High to Power Up
SLEEPN Pulse Width
SLEEPN Pulse Rejection
I/O
LOCK
Descriptions
Parameter
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
t
PWRDN
t
WSLEEPN
3-16
or t
Default duty cycle selected
Fout ≥ 100MHz
Fout < 100MHz
Divider ratio = integer
At 90% or 10%
90% to 90%
10% to 10%
All
LCMXO256
LCMXO640
LCMXO1200
LCMXO2280
All
All
WAWAKE
Device
Power Down Mode
Conditions
DC and Switching Characteristics
3
MachXO Family Data Sheet
t
PWRUP
Min.
400
3
—
—
—
—
—
—
0.195
Min.
420
100
0.5
0.5
25
25
25
45
10
—
—
—
—
—
—
—
1
Typ.
—
—
—
—
—
—
—
+/-120
+/-200
+/-200
Max.
0.05
0.02
420
420
210
840
150
450
55
10
—
—
—
—
—
1000
Max
400
400
600
800
100
—
Units
UIPP
MHz
MHz
MHz
MHz
MHz
UI
ps
ps
ns
µs
ps
ps
ns
ns
ns
ns
%
Units
ns
µs
µs
µs
µs
ns
ns