ATA6025 ATMEL Corporation, ATA6025 Datasheet - Page 4

• Manufacturer Part Number: ATA6025
• Description: Ata6025 Watchdog Ic
• Manufacturer: ATMEL Corporation

3.6
3.7
3.8
4
Time Delay
Output NOTL
Test Mode
ATA6025
The internal time delay is generated by an up/down counter. The clock for the counter is dis-
abled if the voltage at the supply pin VB < 5.76V. In this case, the internal signal VBOK will be
set to low and the output NOTL is directly switched to low.
The direction of counting is set by the watchdog or VCC over- and undervoltage detection. If the
VCC monitoring detects an undervoltage condition, the failure signal VCCL (VCC low voltage) is
set and starts the up counter. If the VCC monitoring detects an overvoltage condition, the failure
signal VCCH (VCC high voltage) is set and starts the up counter.
A failure at the watchdog sets the internal fwd signal (failure watchdog) to high and starts the up
counter. If the counter’s final value is reached, a Flip Flop is set and switches the output NOTL to
high. If no failure signal is set and the window watchdog has counted successive 16 alternate
WDI edges then the down counter is started. If the counter reaches the zero value the Flip Flop
receives a reset command and switches the output NOTL off.
The down counter is also started if the voltage at input VKL15 is low and switches the output
NOTL after t
If the voltage at VKL15 is high and if a failure signal is set, the output NOTL switches to high
after the internal time delay.
The output is short circuit protected with a current limitation of ISC
The maximum output voltage is limited to VC
The pin CLK is normally open or connected to GND. If the internal clock frequency is to be
checked, the CLK pin has to be connected with an external resistor Rex = 5 k to a 5V supply.
The measured value is the clock frequency divided by four.
Delay
= 400 ms to low (see
Figure 8-3 on page
NOTL
= 22V (see
10).
Figure 8-4 on page
NOTL
= 15 mA.
10).
4716C–AUTO–09/05