ATA6025 ATMEL Corporation, ATA6025 Datasheet - Page 3

• Manufacturer Part Number: ATA6025
• Description: Ata6025 Watchdog Ic
• Manufacturer: ATMEL Corporation

3. Functional Description
3.1
3.2
3.3
3.4
3.5
4716C–AUTO–09/05
Voltage Supply
Oscillator
VKL15 Monitoring
VCC Over-/Undervoltage
Watchdog
The IC can be supplied directly from V
old of V
the IC is completely disabled and the output NOTL is switched off in all cases (see
page
If the voltage at pin VKL15 is low, the IC is in standby mode and reduces the current consump-
tion at pin VB < 100 µA.
The frequency f
internal capacitor. Thus, it is possible to vary the oscillator frequency between 4 kHz and 24 kHz.
This input is used to monitor the battery voltage at ignition pin VKL15. If the voltage
V
switches to standby mode. During standby mode the monitor function is disabled and the output
NOTL is switched off after the time delay t
If the output NOTL is switched on and the voltage at VKL15 switches suddenly to low, the inter-
nal timer starts and switches the NOTL off after a time delay of t
Via the VCC input an external 5V voltage regulator is continuously monitored. If the voltage at
pin VCC exceeds the voltage of VCC
pin VCC decreases to a value below VCC
(see
This failure bit starts the internal counter and switches the output NOTL on after the time delay
of typically t
If the VCC voltage is inside the tolerance VCC
and the internal counter counts back to zero. After a time delay of typically t
output NOTL is switched off again.
A microcontroller can be monitored by a digital window watchdog which accepts an incoming
trigger signal T
between two alternate edges exceeds the time window of To
dog signal, the failure signal fwd (failure watchdog) is set. In case the pulse width T
two alternate edges falls below the time window of Tu
watchdog) is also set. With this fwd signal the internal up counter is activated and after a time
delay of t
If NOTL is high, 16 successive correct watchdog signals T
Tu
the down counter. After a time delay of t
Figure 8-2 on page
KL15lo
WD
Figure 8-1 on page
10).
< T
< 1.8V, the internal signal NVKL15 is set to high (see
VBlo
WD
Delay
= 5.76 V, the internal signal V
Delay
< To
= 400 ms, the output NOTL is switched to high.
WD
= 400 ms.
CLK
WD
of a constant frequency at pin WD for correct operation. If the pulse width T
9).
of the internal oscillator is defined by the external resistor RSET and the
are needed to create the internal signal nfwd (no failure watchdog) to start
9).
hon
battery
> 6.3V, the failure bit VCCH is set high. If the voltage at
Delay
BOK
lon
Delay
. If the voltage at the VB pin is lower than the thresh-
< 4V, the internal failure bit VCCL will be set to high
= 400 ms, the output NOTL is switched to low (see
is set to low. If V
.
loff
< V
VCC
WD
< VCC
< 2.6 ms, the failure signal fwd (failure
WD
BOK
Figure 8-3 on page
hoff
Delay
> 8.9 ms or if there is no watch-
WD
is low, the monitor function of
the failure signal will be reset
= 400 ms.
within the pulse width of
Delay
ATA6025
= 400 ms, the
Figure 8-3 on
10). The IC
WD
between
WD
3