ATA6613 ATMEL Corporation, ATA6613 Datasheet - Page 213

• Manufacturer Part Number: ATA6613
• Description: Ata6613
• Manufacturer: ATMEL Corporation

6.17.9.2
9111C–AUTO–02/08
USART Control and Status Register n A – UCSRnA
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-
ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter
will load the data into the Transmit Shift Register when the Shift Register is empty. Then the
data will be serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the
receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Mod-
ify-Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions
(SBIC and SBIS), since these also will change the state of the FIFO.
• Bit 7 – RXCn: USART Receive Complete
• Bit 6 – TXCn: USART Transmit Complete
• Bit 5 – UDREn: USART Data Register Empty
• Bit 4 – FEn: Frame Error
• Bit 3 – DORn: Data OverRun
Initial Value
Read/Write
This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled,
the receive buffer will be flushed and consequently the RXCn bit will become zero. The
RXCn Flag can be used to generate a Receive Complete interrupt (see description of the
RXCIEn bit).
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out
and there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag
bit is automatically cleared when a transmit complete interrupt is executed, or it can be
cleared by writing a one to its bit location. The TXCn Flag can generate a Transmit Com-
plete interrupt (see description of the TXCIEn bit).
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If
UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can
generate a Data Register Empty interrupt (see description of the UDRIEn bit).
UDREn is set after a reset to indicate that the Transmitter is ready.
This bit is set if the next character in the receive buffer had a Frame Error when received.
I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid
until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data
is one. Always set this bit to zero when writing to UCSRnA.
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the
receive buffer is full (two characters), it is a new character waiting in the Receive Shift Reg-
ister, and a new start bit is detected. This bit is valid until the receive buffer (UDRn) is read.
Always set this bit to zero when writing to UCSRnA.
Bit
RXCn
R
7
0
TXCn
R/W
6
0
UDREn
R
5
1
FEn
R
4
0
DORn
R
3
0
ATA6612/ATA6613
UPEn
R
2
0
U2Xn
R/W
1
0
MPCMn
R/W
0
0
UCSRnA
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