78Q2132 TDK Corp., 78Q2132 Datasheet - Page 17

• Manufacturer Part Number: 78Q2132
• Description: 1/10base-t Homepna/ethernet Transceiver
• Manufacturer: TDK Corp.

MR16 - VENDOR SPECIFIC REGISTER (continued)
MR17 - INTERRUPT CONTROL/STATUS REGISTER
The Interrupt Control/Status Register provides the means for controlling and observing the events that trigger an
interrupt on the INTR pin. This register can also be used in a polling mode via the MII serial interface as a means
to observe key events within the PHY via one register address. These bits are cleared after the register is read.
Bits 8-15 of this register, when set to logic one, enable their corresponding bit in the lower byte to signal an
interrupt on the INTR pin. The level of this interrupt can be set via MR16.14.
BIT
17.15
17.14
17.13
17.12
17.11
17.10
17.9
17.8
17.7
16.3:2
16.6
16.5
16.4
16.1
16.0
BIT
SYMBOL
JABBER IE
RXER IE
PRX IE
PDF IE
LP-ACK IE
LS-CHG IE
RFAULT IE
ANEG-COMP IE
JABBER INT
GPIO0_DIR
SYMBOL
RVSPOL
MII_EN
RSVD
RSVD
APOL
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
RC, 0
TYPE
R, (W), 0
R, W, 1
R, W, 0
R,W,0
TYPE
R, 0
R, 0
DESCRIPTION
Jabber Interrupt Enable
Receive Error Interrupt Enable: Reserved for 100Base-TX
Page Received Interrupt Enable
Parallel Detect Fault Interrupt Enable
Link Partner Acknowledge Interrupt Enable
Link Status Change Interrupt Enable
Remote Fault Interrupt Enable
Auto-negotiation Complete Interrupt Enable
Jabber Interrupt: This bit is set when a jabber event is indicated by the
10baseT circuitry.
DESCRIPTION
GENERAL PURPOSE I/O 0 DIRECTION BIT: Setting this bit
configures the GPIO0 pin as an input. Resetting it configures GPIO0
as an output.
AUTO POLARITY: During auto-negotiation and 10BASE-T mode,
the 78Q2132 is able to automatically invert the received signal - both
the Manchester data and link pulses - if necessary. Setting this bit
disables this feature.
REVERSE POLARITY: The reverse polarity is detected through 8
inverted 10BASE-T link. When the reverse polarity is detected, the
78Q2132 will invert the receive data path and set this bit to logic one
if the feature is not disabled. If APOL is a logic 1, then this bit is
write-able. Setting this bit forces the polarity to be reversed.
RESERVED. Must be zero.
MII ENABLE: When this bit is high, the MII port mode is selected.
When low, its meaning is dependent on the mode of the chip as
shown below:
Mode
HomeLAN
10BT
RESERVED. Must be zero.
17
Hi
MII
MII
Function
HomePNA/Ethernet Transceiver
GPSI
MII
Lo
1/10BASE-TX
78Q2132