78Q2132 TDK Corp., 78Q2132 Datasheet - Page 16

• Manufacturer Part Number: 78Q2132
• Description: 1/10base-t Homepna/ethernet Transceiver
• Manufacturer: TDK Corp.

78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
REGISTER DESCRIPTION
MR6 - AUTO-NEGOTIATION EXPANSION REGISTER
MR16 - VENDOR SPECIFIC REGISTER
16.15
16.14
16.13
16.12
16.11
16.10
6.15:5
16.9
16.8
16.7
BIT
BIT
6.4
6.3
6.2
6.1
6.0
GPIO1_DAT
GPIO0_DAT
LOOPBACK
GPIO1_DIR
INT LEVEL
SQE TEST
NATURAL
LPANEGA
SYMBOL
SYMBOL
INHIBIT
LPNPA
RSVD
RSVD
RSVD
RSVD
PDF
NPA
PRX
R, W, (0)
R,0,RC
R,0,RC
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 1
R, W, 0
TYPE
TYPE
(continued)
R, 0
R, 0
R, 0
R,0
R,0
R0
DESCRIPTION
RESERVED: This bit is permanently tied low
PARALLEL DETECTION FAULT: When set, it indicates that more
than one technology was detected during link up. This bit is cleared
when read.
LINK PARTNER NEXT PAGE ABLE: When set, it indicates that the
link partner supports the next page function.
NEXT PAGE ABLE: Not supported; permanently tied low
PAGE RECEIVED: Set when a properly matched link code word
has been received into the Auto-negotiation Link Partner. This bit is
cleared when read.
LINK PARTNER AUTO-NEGOTIATION ABLE:
indicates that the link partner is able to participate in the auto-
negotiation function.
DESCRIPTION
Reserved
When this bit is a zero, the INTR pin is forced low to signal an
interrupt. Setting this bit causes the INTR pin to be forced high to
signal an interrupt.
RESERVED
RESERVED
Setting this bit disables 10BASE-T SQE testing. By default, when
this bit is a zero, the SQE test is performed by generating a COL
pulse following the completion of a packet transmission.
Setting this bit causes transmitted data on TXD to be automatically
looped back to the RXD receive signals when 10BASE-T mode is
enabled. In HomePNA mode, the default is 1 and the transmit
symbol NT_SYM is looped back into the receive symbol RD_SYM.
GENERAL PURPOSE I/O 1 DATA BIT: When the GPIO_DIR is set,
this bit reflects the value of the GPIO1 pin. When the GPIO1_DIR is
reset, the value of this bit is driven onto the GPIO1 pin.
GENERAL PURPOSE I/O 1 DIRECTION BIT: Setting this bit
configures the GPIO1 pin as an input. Resetting configures GPOI_1
as an output.
GENERAL PURPOSE I/O 0 DATA BIT: When the GPIO0_DIR is set,
this bit reflects the value of the GPIO0 pin. When the GPIO0_DIR is
reset, the value of this bit is driven onto the GPIO0 pin.
16
When set, it