1ED020I12FA Infineon Technologies Corporation, 1ED020I12FA Datasheet - Page 8

• Manufacturer Part Number: 1ED020I12FA
• Description: Single Igbt Driver Ic
• Manufacturer: Infineon Technologies Corporation

3.2
GND1
Ground connection of the input side.
IN+ Non-inverting driver input
IN+ control signal for the driver output if IN- is set to low.
(The IGBT is on if IN+ = high and IN- = low)
A minimum pulse width is defined to make the IC robust
against glitches at IN+. An internal Pull-Down-Resistor
ensures IGBT Off-State.
IN- Inverting driver input
IN- control signal for driver output if IN+ is set to high.
(IGBT is on if IN- = low and IN+ = high)
A minimum pulse width is defined to make the IC robust
against glitches at IN-. An internal Pull-Up-Resistor ensures
IGBT Off-State.
/RST (Reset) input
Function 1: Enable/shutdown of the input chip. (The IGBT is
off if /RST = low). A minimum pulse width is defined to
make the IC robust against glitches at IN-.
3
3.1
Pin
Datasheet
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
Symbol
VEE2
VEE2
DESAT
GND2
NC
VCC2
OUT
CLAMP
VEE2
VEE2
GND1
GND1
IN+
IN-
RDY
FLT
RST
VCC1
GND1
GND1
Pin Functionality
Pin Configuration and Functionality
Pin Configuration
Function
Negative power supply output side
Negative power supply output side
Desaturation protection
Signal ground output side
Not connected
Positive power supply output side
Driver output
Miller clamping
Negative power supply output side
Negative power supply output side
Signal ground input side
Signal ground input side
Non inverted driver input
Inverted driver input
Ready output
Fault output
Reset input
Positive power supply input side
Signal ground input side
Signal ground input side
8
Function 2: Resets the DESAT-FAULT-state of the chip if
/RST is low for a time T
An internal Pull-Up-Resistor is used to ensure FLT status
output.
/FLT (Fault output)
Open-drain output to report a desaturation error of the IGBT
(FLT is low if desaturation occurs)
RDY (Ready status)
Open-drain output to report the correct operation of the
device. (RDY = high if both chips are above the UVLO level
and the internal chip transmission is faultless)
VCC1
5V power supply of the input chip
VEE2
Negative power supply pins of the output chip. If no negative
supply voltage is available, both pins have to be connected to
GND2.
1
2
3
4
5
6
7
8
9
10
Figure 4: PG-DSO-20-55
VEE2
VEE2
DESAT
GND2
NC
VCC2
OUT
CLAMP
VEE2
VEE2
RST
.
GND1
GND1
GND1
GND1
VCC1
/RST
RDY
/FLT
Version 2.1, 2009-11-24
IN+
IN-
EICEDRIVER®
20
19
18
17
16
15
14
13
12
11
1ED020I12FA