IDT72T36115 Integrated Device Technology, IDT72T36115 Datasheet - Page 33

• Manufacturer Part Number: IDT72T36115
• Description: 128k X 36 Terasync Fifo, 2.5v - Best Value!
• Manufacturer: Integrated Device Technology

NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
1149.1) for the full state diagram
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
normal operation of the IC. The TAP controller state machine is designed in such
a way that, no matter what the initial state of the controller is, the Test-Logic-Reset
state can be entered by holding TMS at high and pulsing TCK five times. This
is the reason why the Test Reset (TRST) pin is optional.
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Data Path or the Select-IR-Scan state is made.
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Test-Logic-Reset All test logic is disabled in this controller state enabling the
Run-Test-Idle In this controller state, the test logic in the IC is active only if
Select-DR-Scan This is a controller state where the decision to enter the
Select-IR-Scan This is a controller state where the decision to enter the
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
All state transitions within the TAP controller occur at the rising edge of the
Input = TMS
1
0
Test-Logic
Run-Test/
Reset
Idle
0
Figure 8. TAP Controller State Diagram
1
1
0
1
Update-DR
Capture-DR
Pause-DR
Exit2-DR
DR-Scan
Shift-DR
EXit1-DR
Select-
33
0
0
0
1
1
1
0
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
IR state or Update-IR state is made.
register to be temporarily halted.
IR state or Update-IR state is made.
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
registers selected by the current instruction on the rising edge of TCK.
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
Capture-IR In this controller state, the shift register bank in the Instruction
Shift-IR In this controller state, the instruction register gets connected
Exit1-IR This is a controller state where a decision to enter either the Pause-
Pause-IR This state is provided in order to allow the shifting of instruction
Exit2-DR This is a controller state where a decision to enter either the Shift-
Update-IR In this controller state, the instruction in the instruction register is
Capture-DR In this controller state, the data is parallel loaded in to the data
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
0
0
1
1
0
1
1
1
1
1
Capture-IR
Update-IR
Pause-IR
Exit2-IR
IR-Scan
Exit1-IR
Shift-IR
Select-
1
0
0
0
0
5907 drw13
0
0
COMMERCIAL AND INDUSTRIAL
1
TEMPERATURE RANGES
JANUARY 11, 2007