IDT72T36115 Integrated Device Technology, IDT72T36115 Datasheet - Page 22

• Manufacturer Part Number: IDT72T36115
• Description: 128k X 36 Terasync Fifo, 2.5v - Best Value!
• Manufacturer: Integrated Device Technology

72T36105/72T36115/72T36125, 2 enabled read cycles are required to read
the offset registers, (1 per offset). Data on the outputs Qn are read from the Empty
Offset Register on the first LOW-to-HIGH transition of RCLK. Upon the second
LOW-to-HIGH transition of RCLK, data are read from the Full Offset Register.
The third transition of RCLK reads, once again, from the Empty Offset Register.
72T36105, 2 enabled read cycles are required to read the offset registers, (1
per offset). Data on the outputs Qn are read from the Empty Offset Register on
the first LOW-to-HIGH transition of RCLK. Upon the second LOW-to-HIGH
transition of RCLK, data are read from the Full Offset Register. The third transition
of RCLK reads, once again, from the Empty Offset Register.
read the offset registers, (2 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 2
from the Empty Offset Register MSB. Upon the 3
RCLK data on the outputs Qn are read from the Full Offset Register LSB. Upon
the 4
the Full Offset Register MSB. The 5
the outputs Qn are once again read from the Empty Offset Register LSB.
read the offset registers, (2 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 2
from the Empty Offset Register MSB. Upon the 3
RCLK data on the outputs Qn are read from the Full Offset Register LSB. Upon
the 4
the Full Offset Register MSB. The 5
the outputs Qn are once again read from the Empty Offset Register LSB.
read the offset registers, (3 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 3
from the Empty Offset Register MSB. Upon the 4
RCLK data on the outputs Qn are read from the Full Offset Register LSB. Upon
the 6
the Full Offset Register MSB. The 7
the outputs Qn are once again read from the Empty Offset Register LSB. See
Figure 3, Programmable Flag Offset Programming Sequence. See Figure
22, Parallel Read of Programmable Flag Registers, for the timing diagram for
this mode.
writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT FROM MARK OPERATION
starting at a user-selected position. The FIFO is first put into retransmit mode that
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
When a 36 bit output bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
When an 18 bit output bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
For the IDT72T36115/72T36125, 4 enabled read cycles are required to
When a 9 bit output bus width is used:
For the IDT72T36115/72T36125, 4 enabled read cycles are required to
For the IDT72T36115/72T36125, 6 enabled read cycles are required to
It is permissible to interrupt the offset register read sequence with reads or
The Retransmit from Mark feature allows FIFO data to be read repeatedly
Parallel reading of the offset registers is always permitted regardless of
th
th
th
LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
nd
nd
rd
LOW-to-HIGH transition of RCLK data on the outputs Qn are read
LOW-to-HIGH transition of RCLK data on the outputs Qn are read
LOW-to-HIGH transition of RCLK data on the outputs Qn are read
th
th
th
LOW-to-HIGH transition of RCLK data on
LOW-to-HIGH transition of RCLK data on
LOW-to-HIGH transition of RCLK data on
rd
rd
th
LOW-to-HIGH transition of
LOW-to-HIGH transition of
LOW-to-HIGH transition of
22
will ‘mark’ a beginning word and also set a pointer that will prevent ongoing FIFO
write operations from over-writing retransmit data. The retransmit data can be
read repeatedly any number of times from the ‘marked’ position. The FIFO can
be taken out of retransmit mode at any time to allow normal device operation.
The ‘mark’ position can be selected any number of times, each selection over-
writing the previous mark location. Retransmit operation is available in both IDT
standard and FWFT modes.
to-High transition on RCLK when the ‘MARK’ input is HIGH and EF is HIGH.
The rising RCLK edge ‘marks’ the data present in the FIFO output register as
the first retransmit data. The FIFO remains in retransmit mode until a rising edge
on RCLK occurs while MARK is LOW.
mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK
while the retransmit input (RT) is LOW. REN must be HIGH (reads disabled)
before bringing RT LOW. The device indicates the start of retransmit setup by
setting EF LOW, also preventing reads. When EF goes HIGH, retransmit setup
is complete and read operations may begin starting with the first data at the MARK
location. Since IDT standard mode is selected, every word read including the
first ‘marked’ word following a retransmit setup requires a LOW on REN (read
enabled).
functions, however write operations to the ‘marked’ location will be prevented.
See Figure 18, Retransmit from Mark (IDT standard mode), for the relevant
timing diagram.
edge when the ‘MARK’ input is HIGH and OR is LOW. The rising RCLK edge
‘marks’ the data present in the FIFO output register as the first retransmit data.
The FIFO remains in retransmit mode until a rising RCLK edge occurs while
MARK is LOW.
mode, MARK is HIGH), a retransmit can be initiated by a rising RCLK edge while
the retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before
bringing RT LOW. The device indicates the start of retransmit setup by setting
OR HIGH.
RCLK edge after retransmit setup is complete, (RT goes HIGH), the contents
of the first retransmit location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of REN, a
LOW on REN is not required for the first word. Reading all subsequent words
requires a LOW on REN to enable the rising RCLK edge. See Figure 19,
Retransmit from Mark timing (FWFT mode), for the relevant timing diagram.
and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long
words). Also, once the MARK is set, the write pointer will not increment past the
“marked” location until the MARK is deasserted. This prevents “overwriting”
of retransmit data.
HSTL/LVTTL I/O
LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
control pins are selectable via SHSTL, see Table 5 for details of groupings.
the power consumption (in stand-by mode by utilizing the WCS input).
and are purely device configuration pins.
Both the write port and read port are user selectable between HSTL or
Note, that when the write port is selected for HSTL mode, the user can reduce
All “Static Pins” must be tied to V
During IDT standard mode the FIFO is put into retransmit mode by a Low-
Once a ‘marked’ location has been set (and the device is still in retransmit
Note, write operations may continue as normal during all retransmit
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
Once a marked location has been set (and the device is still in retransmit
When OR goes LOW, retransmit setup is complete and on the next rising
Note, there must be a minimum of 32 bytes of data between the write pointer
CC
COMMERCIAL AND INDUSTRIAL
or GND. These pins are LVTTL only,
TEMPERATURE RANGES
JANUARY 11, 2007