S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 382
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S1D13705
Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13705.pdf
(480 pages)
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4 PC Card to S1D13705 Interface
4.1 Hardware Connections
S1D13705
X27A-G-009-02
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
PC Card socket
D[15:0]
A[16:0]
RESET
WAIT#
CE1#
CE2#
Figure 4-1: Typical Implementation of PC Card to S1D13705 Interface
WE#
OE#
The S1D13705 is interfaced to the PC Card bus with a minimal amount of glue logic. In
this implementation, the address inputs (AB[16:0]) and data bus (DB[15:0] connect directly
to the CPU address (A[16:0]) and data bus (D[15:0]).
The PC Card interface does not provide a bus clock, so one must be supplied for the
S1D13705. Since the bus clock frequency is not critical, nor does it have to be synchronous
to the bus signals, it may be the same as CLKI.
BS# (bus start) is not used by Generic #2 mode but is used to configure the S1D13705 for
either Generic #1 or Generic #2 bus and should be tied high (connected to IO V
RD/WR# is also not used by Generic #2 bus and should be tied high (connected to IO V
The following diagram shows a typical implementation of the PC Card to S1D13705
interface.
15K pull-up
Oscillator
IO V
IO V
DD
DD
Epson Research and Development
RD/WR#
RESET#
BS#
AB[16:0]
DB[15:0]
WAIT#
RD#
WE0#
WE1#
BUSCLK
CLKI
CS#
Interfacing to the PC Card Bus
S1D13705
Vancouver Design Center
Issue Date: 01/02/13
DD
).
DD
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