STEL-1209/CE Intel, STEL-1209/CE Datasheet - Page 4

• Manufacturer Part Number: STEL-1209/CE
• Description: BPSK/QPSK/16 QAM Burst Modulator Assembly
• Manufacturer: Intel

SPECIFICATIONS
Output Frequency Range:
5 MHz to 65 MHz using an external clock frequency of
165 MHz (or up to 40 MHz using the provided on-
board clock at 102.4 MHz).
Resolution:
10 Hz @ f
J2 -- Master Clock Input:
To use the on-board 102.4 MHz crystal oscillator, jump
pin 2 and pin 3 on JP4.
To use an external master clock, jump pin 1 and pin 2
on JP4.
Maximum Frequency, f
BNC connector, input power at +10 dBm to +13 dBm,
A.C. coupled, 50 Ohms
J16 -- External TCLK Input:
BNC connector, HCMOS levels.
J7 -- Aux. Output:
SMB connector for single ended DAC output.
Transformer T1 is used to do the double-to-single
ended conversion.
JP3 is used to route the single ended output to either J7
or J5.
J8 -- SYNC Output:
BNC connector, HCMOS levels
Pulse covering the period of bursting symbols. This
signal (equivalent to DATAENO inverted) can be used
as a scope trigger.
J5 -- IF Output:
BNC connector, 75 Ohms.
Output power: + 0 dBm @ default settings
Return loss: 15 dB
Stop band: 30 dB at 85 MHz with 65 MHz LPF
Note: The output level of the DAC falls as the carrier
frequency rises according to the equation:
Note: The on-board low pass filter (LPF) cut-off
frequency can be selected between 42 MHz or 65 MHz
by properly configuring JP5 and JP6.
V
where : f
OUT
STEL-1209
CLK
V
OUT(DC)
165 MHz (24 bits)
f
CLK
f
OUT
f
(sine f)
CLK(MAX)
= 165 MHz
4
J1 -- External Serial Data Input:
BNC connector, HCMOS levels.
Output Level Control:
The output level can be controlled over a range of 15 dB
in 1 dB steps by means of the control software supplied.
P2 -- RS-232C Control Interface:
Connector Type: 9-pin Subminiature ‘D’, female (DCE).
Pin 2 TXD
Pin 5 GND
Power Requirements (Typical):
JP1, pin 1:
JP1, pin 2:
JP1, pin 3:
JP1, pin 4:
Temperature Range, Ambient:
0-70° Operating
Connector J3:
Pin 1 NC
Pin 3 AUXCLK
Pin 5 SCRMEN
Pin 7 TCLK
Pin 9 TSDATA
Pin 11 DSB
Pin 13 TXCLK_B
Pin 15 BURSTGATE_B
Pin 17 DATAENO
Pin 19 BITCLK
Connector J4:
Pin 1 NC
Pin 3 EXT_TCLK_B
Pin 5 uP_WRB
Pin 7 CLKEN_LOW
Pin 9 BURST
Pin 11 PREAMBLE_SRAM Pin 12 LOAD_RUN
Pin 13 (SPARE)
Pin 15 Burst/Done
Pin 17 VCC (SPARE)
Pin 19 NCO_LOAD
Pin 3 RXD
Pin 7 GND
-5 volts ±5%, 10 mA
Analog GND
Digital GND
+5 volts ±5%, 330 mA
(@ fclk = 100 MHz)
Pin 2
Pin 4
Pin 6
Pin 8
Pin 10 WRB
Pin 12 DIFFEN
Pin 14 TXDATA_B
Pin 16 CKSUM
Pin 18 SYMPLS
Pin 20 GND
Pin 2
Pin 4
Pin 6
Pin 8
Pin 10 (SPARE)
Pin 14 uP_BURSTGATE
Pin 16 (SPARE)
Pin 18 VCC (SPARE)
Pin 20 GND
NC
RDSLEN
CLKEN
DATAEN
NC
SYMCLK
uP_RDB
(SPARE)