STEL-1209/CE Intel, STEL-1209/CE Datasheet - Page 17

• Manufacturer Part Number: STEL-1209/CE
• Description: BPSK/QPSK/16 QAM Burst Modulator Assembly
• Manufacturer: Intel

Slave Mode, QPSK
Burst Timing: Full Burst
NOTES:
PIN
19
17
26
18
39
70
29
32
42
(1)
(2)
(3)
(A) First data bit transition on falling edge of TCLK (first of 14 preamble symbols). The data will be valid on the next rising edge of
(B) CLKEN rises on the same falling edge of TCLK that the data starts on. CLKEN is allowed to rise any time earlier than shown.
(C) DATAEN rises on the first rising edge of TCLK (middle of the first preamble bit).
(D) DATAENO rises on the falling edge of TCLK (at the end of the second symbol).
(E) DIFFEN rises on the rising edge of TCLK one symbol before the first user data symbol.
(F) User data bits change on the falling edge of TCLK and must be valid during the next rising edge of TCLK.
(G) End of user data. Note that the data is allowed to go away immediately after it is latched in by the rising of TCLK which
(H) DIFFEN goes low on rising edge of TCLK (last user data symbol).
(I)
(J)
(K) DATAENO stays high until the 13th SYMPLS after DATAEN goes low.
(L) RDSLEN and SCRMEN go high on the first rising edge of TCLK in the User Data.
(M) RDSLEN goes low on the rising edge of TCLK (last user data symbol).
(N) SCRMEN goes low on the rising edge of TCLK (on the cycle of TCLK after the last user data bit).
DATAENO
DIFFEN
SCRMEN
DATAEN
RDSLEN
SYMPLS
TSDATA
All input signals shown are derived from TCLK. Each edge is delayed from a TCLK edge by typically 6 to 18 nsec.
DATAENO does not depend on TCLK but its edges are synchronized to TCLK. TCLK itself can be turned off after DATAENI
goes low.
DATAENO shown at its minimum pipeline delay position. This is achieved by setting bit 6 of Configuration Register 36
zero. Reed-Solomon cannot be used in this mode. If bit 6 is set high, allowing Reed-Solomon an additional pipeline delay of
8 bits is inserted into the data path. This will shift both edges of DATAENO to the right by 8 cycles of TCLK.
If the preamble is not encoded the same as the user data, the DIFFEN control can be toggled in mid transmission as shown.
Otherwise, the DIFFEN control can be held high or low depending on encoding desired.
TCLK.
occurs in the middle of the last user data bit.
DATAEN goes low on rising edge of TCLK (on the cycle of TCLK after the last user data bit).
CLKEN must stay high until any time on or after the point where DATAENO goes low.
TCLK
CLKEN
NAME
(2)
(1)
(3)
(A)
(B)
(C)
(D)
Preamble
(E)
(F)
(L)
(L)
17
User Data
(M)
(H)
(G)
(N)
(I)
Guard Time
WCP 52934.c -5/7/97
(K)
(J)
STEL-1209
H
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