STE2002 STMicroelectronics, STE2002 Datasheet - Page 21

• Manufacturer Part Number: STE2002
• Description: 81 x 128 SINGLE CHIP LCD CONTROLLER / DRIVER
• Manufacturer: STMicroelectronics

STE2002
condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the ac-
knowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass
(COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system
SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin
Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2002 will not be able
to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode
that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is nec-
essary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid
LOW level.
2
To be compliant with the I
C-bus Hs-mode specification the STE2002 is able to detect the special sequence
"S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without
detecting the master code.
Figure 29. Bit transfer and START,STOP conditions definition
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CHANGE OF
STOP
CONDITION
DATA ALLOWED
CONDITION
D00IN1151
2
Figure 30. Acknowledgment on the I
C-bus
CLOCK PULSE FOR
START
ACKNOWLEDGEMENT
SCLK FROM
MASTER
1
2
8
9
DATA OUTPUT
MSB
LSB
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
D00IN1152
Communication Protocol
2
The STE2002 is an I
C slave. The access to the device is bi-directional since data write and status read are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits (01111). The two least sig-
nificant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or to a logic 1.
To start the communication between the bus master and the slave LCD driver, the master must initiate a START con-
dition. Following this, the master sends an 8-bit byte, shown in Fig. 30, on the SDA bus line (Most significant bit first).
This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/W).
2
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I
C-bus transfer.
Writing Mode.
If the R/W bit is set to logic 0 the STE2002 is set to be a receiver. After the slaves acknowledge one or more
command word follows to define the status of the device.
A command word is composed by two bytes. The first is a control byte which defines the Co and D/C values,
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