STE2004 STMicroelectronics, STE2004 Datasheet - Page 26

• Manufacturer Part Number: STE2004
• Description: 102 x 65 SINGLE CHIP LCD CONTROLLER/DRIVER
• Manufacturer: STMicroelectronics

STE2004
4
To provide the widest flexibility and ease of use the STE2004 features Six different methods for interfacing
the host Controller. To select the desired interface the SEL1, SEL2 and SEL3 pads need to be connected
to a logic LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused inter-
faces must be connected to GND.
All interfaces are working while the STE2004 is in Power Down.
Table 7.
4.1 I
The I
and High Speed Mode (3.4MHz).
This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for
data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a
positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, de-
fine the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High,
defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the High period of the clock signal. The data on the line may be changed during
the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of
data bytes transferred between the start and the stop conditions is not limited. The information is transmit-
ted byte-wide and each receiver acknowledges with the ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device that gets the
signals is called "receiver". The device that controls the message is called "master". The devices that are
controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock
pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also,
a master receiver must generate an acknowledge after the reception of each byte that has been clocked
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BUS INTERFACES
2
2
C interface is a fully complying I
C Interface
SEL3
0
0
0
0
1
1
while the clock line is high will be interpreted as control signals.
SEL2
0
0
1
1
0
0
2
C bus specification, selectable to work in both Fast (400kHz Clock)
SEL1
0
1
0
1
0
1
I
SPI 4 lines 8 bit
SPI 3 lines 8 bit
Serial 3 lines 9 bit
Parallel 8080-series
Parallel 68000-series
2
C
Interface
Read and Write; Fast and
High Speed Mode
Read and Write
Read and Write
Read and Write
Read and Write
Read and Write
Note