IXDD430 IXYS Corporation, IXDD430 Datasheet
IXDD430
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IXDD430 Summary of contents
Page 1
... Enable inputs, both final output stage MOSFETs (NMOS and PMOS) are turned off result, the output of the IXDD430 enters a tristate mode and enables a Soft Turn-Off of the MOSFET when a short circuit is detected. This helps prevent damage that could occur to the MOSFET if it were to be switched off abruptly due to a dv/dt over-voltage transient ...
Page 2
... Figure 1A - IXDD430 (Non Inverting With Enable) Diagram Vcc GND Figure 1B - IXDN430 (Non-Inverting) Diagram Vcc 1K IN GND Vcc 1K IN GND Figure 1D - IXDS430 (Inverting and Non Inverting with Enable) Diagram Vcc 1K IN 400K EN INV GND Note: Out P and Out N are connected together in the 5 lead TO-220 and TO-263 packages. ...
Page 3
... Storage Temperature - 150 o C Lead Temperature (10 sec) 300 o C Electrical Characteristics Unless otherwise noted 8.5V ≤ All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions bol Param eter V High input v oltage IH V Low input v oltage IL V ...
Page 4
... Electrical Characteristics Unless otherwise noted, temperature over -55 All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions. Symbol Parameter V High input voltage IH V Low input voltage IL V Input voltage range IN R Output resistance OH @ Output high R Output resistance OL @ Output Low t Rise time ...
Page 5
... GND Ground Select Under UVSEL Voltage Level * This pin is used only on the IXDD430, and is N/C (not connected) on the IXDI430 and IXDN430. CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when handling and assembling this component. Figure 2 - Characteristics Test Diagram C ...
Page 6
... Load Capacitance (pF) Rise and Fall Times vs. Temperature Fig 5600 pF, Vcc = 18V -60 - Temperature (C) IXDN430 / IXDI430 / IXDD430 / IXDS430 Fig 15000 pF 20 10000 pF 5600 1000 Fig. 6 13V 30 18V 35V 25 20 ...
Page 7
... Supply Current vs. Load Capacitance Vcc = 25V 400 350 2 MHz 1 MHz 300 250 200 500 kHz 150 100 100 kHz 50 50 kHz 10 kHz 0 1000 10000 Load Capacitance (pF) IXDN430 / IXDI430 / IXDD430 / IXDS430 Fig. 10 1000 100 10 0.1 100000 Fig. 12 1000 100 z 0.1 100000 Fig. 14 1000 100 10 0.1 100000 7 Supply Current vs ...
Page 8
... Supply Voltage (V) Fig. 19 Propagation Delay Times vs. Temperature C = 5600pF, Vcc = 18V ONDLY 40 t OFFDLY -60 - Temperature (C) IXDN430 / IXDI430 / IXDD430 / IXDS430 Fig. 16 1000 100 100000 Fig Fig. 20 0.6 0.5 0.4 0.3 0.2 ...
Page 9
... V cc (V) P Channel Output Current vs. Temperature Fig. 25 Vcc = 18V -60 - Temperature (C) IXDN430 / IXDI430 / IXDD430 / IXDS430 Fig. 22 0.25 0.2 0.15 0.1 0. Fig Fig ...
Page 10
... Figure 27 - Typical circuit to decrease di/dt during turn-off Figure 28 - IXDD430 Application Test Diagram One Shot Circuit NOT1 CD4049A Ros 1Mohm Cos 1pF EN IXDD430 VCC VCCA VCC VIN GND - - SUB NAND NOT2 CD4011A CD4049A R Q NOT3 NOR1 CD4049A CD4001A NOR2 CD4001A SR Flip-Flop 10 IXDN430 / IXDI430 / IXDD430 / IXDS430 ...
Page 11
... One Shot circuit between the IXDD430 Input signal and the SRFF restart input. The One Shot will create a pulse on the rise of the IXDD430 input, and this pulse will reset the SRFF outputs to normal operation. When a short circuit occurs, the voltage drop across the low- value, current-sensing resistor, (Rs=0 ...
Page 12
... Figure 29 will cause biased off. This results in Q1 collector being pulled high voltage CMOS logic high output. The high voltage CMOS logical EN output applied to the IXDD430 EN input will enable it, allowing the gate driver to fully function Amp output driver. ...