CS61574-IL Cirrus Logic, Inc., CS61574-IL Datasheet - Page 11

• Manufacturer Part Number: CS61574-IL
• Description: Interface, T1/E1 Line Interface
• Manufacturer: Cirrus Logic, Inc.

Transmit All Ones Select
The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. If Remote
Loopback is in effect, any TAOS request will be
ignored.
DS155PP2
Figure 9. Mask of the Pulse at the 2048 kbps Interface
120
110
100
-10
-20
90
80
50
10
0
Percent of
nominal
peak
voltage
Nominal peak voltage of a mark (pulse)
Peak voltage of a space (no pulse)
Nominal pulse width
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
* When configured with a 0.47 F nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
269 ns
244 ns
194 ns
219 ns
488 ns
Nominal Pulse
Table 4. CCITT G.703 Specifications
For c oax ia l c able,
75
transformer specified
in Application Section.
Receiver
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cable lengths and requires no equalization
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a center-
tapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and data recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCITT REC. G.823.
A block diagram of the receiver is shown in Fig-
ure 10. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0 in-
puts).
The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
0 0.237 V
2.37 V
loa d
0.95 to 1.05*
0.95 to 1.05*
a nd
244 ns
For shielded twisted
pair, 120
transformer specified
in Application Section.
0 0.30 V
3 V
load and
CS61577
11