CS61574A Cirrus Logic, Inc., CS61574A Datasheet - Page 4

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CS61574A

Manufacturer Part Number
CS61574A
Description
T1/E1 LINE INTERFACE
Manufacturer
Cirrus Logic, Inc.
Datasheet

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ANALOG SPECIFICATIONS
Notes: 20. For input amplitude of 1.2 V
4
Receiver
RTIP/RRING Input Impedance
Sensitivity Below DSX (0dB = 2.4V)
Data Decision Threshold
Allowable Consecutive Zeros before LOS
Receiver Input Jitter Tolerance
Loss of Signal Threshold
21. For input amplitude of 0.5 V
22. For input amplitude of 1.05 V
23. Jitter tolerance increases at lower frequencies. See Figure 11.
24. The analog input squelch circuit shall operate when the input signal amplitude above ground on the
RTIP and RRING pins falls within the range of 0.25V to 0.50V. Operation of the squelch results in
the recovery of zeros. During receive LOS, the RPOS, RNEG or RDATA outputs are forced low.
T1, DSX-1
T1, DSX-1
T1, FCC Part 68 and E1
10kHz - 100kHz
2kHz
10Hz and below
Parameter
pk
pk
pk
(TA = -40 C to 85 C; TV+, RV+ = 5.0V 5%; GND = 0V)
to 4.14 V
to 1.2 V
to 3.3 V
pk
pk
pk
(Note 20)
(Note 21)
(Note 22)
(Note 23)
(Note 24)
and from 4.14 V
.
.
-13.6
0.25
Min
500
160
300
0.4
6.0
60
53
45
-
pk
to RV+.
0.30
Typ
175
50k
65
65
50
-
-
-
-
-
CS61574A CS61575
Max
0.50
190
70
77
55
-
-
-
-
-
-
% of peak
% of peak
% of peak
DS154F2
Units
bits
mV
dB
UI
UI
UI
V

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