CS61305A-IL1 Cirrus Logic, Inc., CS61305A-IL1 Datasheet - Page 17

• Manufacturer Part Number: CS61305A-IL1
• Description: T1/E1 line interface
• Manufacturer: Cirrus Logic, Inc.

SDO
host controller can be used to control operational
characteristics and monitor device status. The se-
rial port read/write timing is independent of the
system transmit and receive timing.
Data transfers are initiated by taking the chip se-
lect input, CS, low (CS must initially be high).
Address and input data bits are clocked in on the
rising edge of SCLK. The clock edge on which
output data is stable and valid is determined by
CLKE as shown in Table 5. Data transfers are ter-
minated by setting CS high. CS may go high no
sooner than 50 ns after the rising edge of the
SCLK cycle corresponding to the last write bit.
For a serial data read, CS may go high any time
to terminate the output.
Figure 13 shows the timing relationships for data
transfers when CLKE = 1. When CLKE = 1, data
bit D7 is held until the falling edge of the 16th
clock cycle. When CLKE = 0, data bit D7 is held
until the rising edge of the 17th clock cycle. SDO
goes to the high impedance state when the serial
port is being written (R/W = 0), or if CS goes
high, or at the end of the hold period of data bit
D7.
An address/command byte, shown in Table 9,
precedes the data byte. The first bit of the ad-
dress/command byte determines whether a read
or a write is requested. The next six bits contain
the address. The line interface responds to address
16 (0010000). The last bit is ignored.
DS157PP3
CS
SCLK
SDI
R/W
0
Address/Command Byte
0
0
Figure 13. Input/Output Timing
0
1
0
Note:
During a write cycle (R/W = 0), data is written to
the input data register on the eight clock cycles
immediately following the address/command
byte. The input data format over SDI is shown in
Table 10.
Note:
Bits D0 and D1 are used to clear an interrupt is-
sued from the INT pin, which occurs in response
to a loss of signal or a problem with the output
driver.
Writing a "1" to either "Clear LOS" or "Clear
DPM" over the serial interface has three effects:
X
Bit
Bit
D0
D1
D2
D3
D4
D5
D6
D7
0
1
2
3
4
5
6
7
D0
D0
Bit 0 is the first bit input (LSB).
Bit D0 is the first bit input (LSB).
Designation
Designation
Table 9. Address/Command Byte
clr DPM
RLOOP
clr LOS
LLOOP
D1
D1
ADD0
ADD1
ADD2
ADD3
ADD4
LEN0
LEN1
LEN2
TAOS
R/W
Table 10. Input Data Register
X
-
D2
D2
Data Input/Output
Read/Write Select; 0 = write, 1 = read
LSB of address, Must be 0
Must be 0
Must be 0
Must be 0
Must be 1
Reserved - Must be 0
Don’t Care
Clear Loss of Signal
Clear Driver Performance Monitor
Bit 0 - Line Length Select
Bit 1 - Line Length Select
Bit 2 - Line Lenght Select
Remote Loopback
Local Loopback
Transmit All Ones Select
D3
D3
D4
D4
Description
Description
CS61305A
D5
D5
D6
D6
D7
D7
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