CS61305A-IL1 Cirrus Logic, Inc., CS61305A-IL1 Datasheet - Page 12

• Manufacturer Part Number: CS61305A-IL1
• Description: T1/E1 line interface
• Manufacturer: Cirrus Logic, Inc.

written into the jitter attenuator’s FIFO by TCLK.
The rate at which data is read out of the FIFO and
transmitted is determined by the oscillator. Logic
circuits adjust the capacitive loading on the crys-
tal to set its oscillation frequency to the average
of the TCLK frequency. Signal jitter is absorbed
in the FIFO.
Jitter Tolerance of Jitter Attenuator
The FIFO in the jitter attenuator is designed to
neither overflow nor underflow. If the jitter am-
plitude becomes very large, the read and write
pointers may get very close together. Should the
pointers attempt to cross, the oscillator’s divide
by four circuit adjusts by performing a divide by
3 1/2 or divide by 4 1/2 to prevent the overflow
or underflow. When a divide by 3 1/2 or 4 1/2
occurs, the data bit will be driven on to the line
either an eighth bit period early or an eighth bit
period late.
The FIFO of the jitter attenuator in the transmit
path is 192 bits deep. This FIFO will typically be
near the half full point under normal operating
conditions, buffering about 96 bits of data. The
number of bits actually buffered depends on the
relationship of the nominal TCLK frequency to
the center frequency of the crystal oscillator. As
these frequencies deviate, a few bits of FIFO
depth will be lost.
TCLK can have gaps or bursts. As long as the gap
or burst is less than the remaining FIFO depth,
normal operation will continue. For example, if
the nominal TCLK frequency was less than the
oscillator’s center frequency by 40 Hz. The FIFO
will operate 3-4 bits off center or 92 bits full. A
gap in TCLK of 80 cycles would empty the FIFO
by 80 bits but would still not envoke the divide
by 4 1/2 circuitry, as about 12 bits would remain
in the FIFO.
The crystal frequency must be 4 times the nomi-
nal signal frequency: 6.176 MHz for 1.544 MHz
operation; 8.192 MHz for 2.048 MHz applica-
12
tions. Internal capacitors load the crystal, control-
ling the oscillation frequency. The crystal must be
designed so that over operating temperature, the
oscillator frequency range exceeds the system fre-
quency tolerance. Crystal Semiconductor offers
the CXT6176 & CXT8192 crystals, which yield
optimum performance with the CS61305A.
Receiver
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of cable
lengths and requires no equalization or ALBO
(Automatic Line Build Out) circuits. The signal is
received on both ends of a center-tapped, center-
grounded transformer. The transformer is
center-tapped on the IC side. The clock and data
recovery circuit exceeds the jitter tolerance speci-
fications of Publications 43802, 43801, 62411
amended, TR-TSY-000170, and CCITT REC.
G.823.
A block diagram of the receiver is shown in Fig-
ure 11. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0).
The receiver uses an edge detector and a continu-
ously calibrated delay line to generate the
recovered clock. The delay line divides its refer-
ence clock, ACLKI or the jitter attenuator’s
oscillator, into 13 equal divisions or phases. Con-
tinuous calibration assures timing accuracy, even
if temperature or power supply voltage fluctuate.
The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
CS61305A
DS157PP3