A3980 Allegro MicroSystems, Inc., A3980 Datasheet - Page 12

• Manufacturer Part Number: A3980
• Description: Automotive DMOS Microstepping Driver with Translator
• Manufacturer: Allegro MicroSystems, Inc.

While the fault persists, the A3980 continues this cycle at
each step command: enabling the outputs for a short period,
and then disabling the outputs. This allows the A3980 to
handle a continuous short circuit without damage. If, while
stepping rapidly, a short circuit appears and no action is
taken, the repeated short-circuit current pulses eventually
cause the temperature of the A3980 to rise and an overtem-
perature fault occurs.
Open Load Fault Operation.
by monitoring the phase current while the motor is in the
Home microstep position, after a time duration of the blank
time plus an internally-generated delay, t
microstep position, each phase current should be 70% of
I
expected current level (less than 35% of I
open load condition is reported on the fi rst step command.
Because the A3980 translator is reset to the Home state at
power-up, an existing open load is detected at the initial step
command. If an open load condition appears while step-
ping, then it is detected after the translator cycles through
the Home state. Although the A3980 continues to drive the
TripMAX
. If the measured current is less than half of this
Automotive DMOS Microstepping Driver with Translator
An open load is detected
SCT
TripMAX
. At the Home
), then an
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
DMOS outputs during an open load condition, it does not
clear the fault fl ags until the next Home state occurs.
Supply Monitors.
monitored to ensure that they are within the correct operat-
ing range. If the main supply exceeds the overvoltage limit,
V
mode in which all low-side DMOS FETs are enabled and all
high-side DMOS FETs are disabled. This allows the A3980
to survive a load dump transient condition that has up to
50 V on VBATT and a duration of up to 500 ms. If the inter-
nal regulator V
tive undervoltage limits (V
set, the DMOS outputs are disabled, and the internal logic is reset
to the power-on state (the translator is set to the Home state).
Diagnostic Fault Flags
conditions are reported using the two fault fl ag outputs.
These are active-low outputs which are coded as shown in
table 2 to discriminate between the fault conditions. When
both fault fl ags are high, no fault exists.
OVB
, the fault fl ags are set and the A3980 enters a safety
REG
or the logic supply V
External and internal supplies are
UVR
or V
(FF1, FF2)
UVD
), then: the fault fl ags are
DD
go below their respec-
.
Diagnostic fault
A3980
12