A3980 Allegro MicroSystems, Inc., A3980 Datasheet - Page 11

• Manufacturer Part Number: A3980
• Description: Automotive DMOS Microstepping Driver with Translator
• Manufacturer: Allegro MicroSystems, Inc.

mixed decay mode, as shown in fi gures 5 through 8. As the
trip point is reached, the A3980 goes into fast decay mode
until the voltage on the RC pin decays to the same level as the
voltage applied to the PFD pin. The duration of time that the
bridge operates in fast decay mode, t
over a range of values from C
R
After this fast decay period, the A3980 switches to slow
decay mode for the remainder of the fi xed off-time period.
Synchronous Rectifi cation
is triggered by an internal fi xed-off-time cycle, load current
recirculates according to the decay mode selected by the
control logic. The synchronous rectifi cation feature turns on
the appropriate FETs during current decay, and effectively
shorts out the body diodes with the low DMOS R
reduces power dissipation signifi cantly, and eliminates the
need for external Schottky diodes. Synchronous rectifi cation
has two modes: Active mode and Disabled mode (described
below).
Active Mode.
at logic low, Active mode is enabled. This mode allows
synchronous rectifi cation to occur, but when a zero current
level is detected, it also prevents reversal of the load current
by turning off synchronous rectifi cation. This prevents the
motor winding from conducting in the reverse direction.
Disabled Mode.
at logic high, Disabled mode takes effect. This mode disables
synchronous rectifi cation. This mode is typically used when
external diodes are required to transfer power dissipation
from the A3980 package to the external diodes.
Shutdown.
an undervoltage fault on VREG, the DMOS outputs of the
A3980 are disabled until the fault condition is removed. In
the case of an overvoltage fault, the sink DMOS FETs are
switched on, and the source FETs off. At power-up, and in
the event of low V
outputs until V
T
= 12 kΩ to 100 kΩ.
t
FD
In the event of an overtemperature fault or
= R
DD
When the input on the SR terminal is set
reaches the minimum level. Once V
T
DD
×
When the input on the SR terminal is set
, the UVLO circuit disables the DMOS
C
T
×
ln[0.6 (V
Automotive DMOS Microstepping Driver with Translator
T
= 470 pF to 1500 pF and from
. When a PWM-off cycle
FD
DD
(ns), is estimated by
⁄ V
PFD
)]
DSON
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DD
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
. This
is
above the minimum level, the translator resets to the Home
state and the DMOS outputs are re-enabled.
Thermal Protection
junction temperature reaches the thermal shutdown value,
typically 170°C. This is intended only to protect the A3980
from failures due to excessive junction temperatures. Ther-
mal protection will not protect the A3980 from continuous
short circuits, and additional fault diagnostics are integrated for
this purpose. Thermal shutdown has a hysteresis of approxi-
mately 15°C.
Diagnostic Features.
circuits that can detect shorts to VBB, shorts to ground, and
shorted or open circuit load. Short circuits are detected by
monitoring the voltage across the driving DMOS FETs and
the open load is detected by monitoring the phase current
when the motor is in the Home microstep position. All fault
detection takes place following a delay after the blank time.
Short to VBB. A short from any of the motor connections
to the battery or VBB connection is detected by monitoring
the voltage across the bottom FETs in each full-bridge. When
the FET is on, the voltage should be no greater than the
V
Short to Ground. A short from any of the motor connec-
tions to ground is detected by monitoring the voltage across
the top FETs in each full-bridge. When the FET is turned
on, the voltage should be no greater than the V
defi ned in the Electrical Characteristics table.
Shorted Load. A short across the load is detected by
monitoring the voltage across both the top and bottom FETs
in each full-bridge.
Short Fault Operation. Because motor capacitance may
cause the measured voltages to show a fault as the full-bridge
switches, voltages are not sampled until after the blank
time plus an internally-generated delay, t
circuit has been detected, all outputs for the faulty phase are
disabled until the next step command. At the next step com-
mand, the outputs are re-enabled and the voltage across the
FET is resampled.
DSLT
value defi ned in the Electrical Characteristics table.
. All drivers are turned off when the
The A3980 includes monitor
SCT
. Once a short
A3980
DSHT
value
11