CS3410 Amphion Semiconductor Ltd., CS3410 Datasheet - Page 6

• Manufacturer Part Number: CS3410
• Description: High Speed Viterbi/TCM Decoder
• Manufacturer: Amphion Semiconductor Ltd.

VITERBI DECODING
To provide a description of the Viterbi decoder, a brief
summary of the main features of its complementary part, the
CS3310 Convolutional Encoder is necessary. The CS3310
provides encoded data in a range of rates including 1/3 and
1/2. Other rates are achievable through internal puncture
circuitry that deletes bits in a predefined pattern from the
symbol stream. Possible data inversion may arise if the
receiver/demodulator circuitry is unable to determine the
rotation/phase relationship of PSK modulated data. To cope
with data inversion, the CS3310 input data stream can be
passed through a Differential Encoder prior to encoding
(Figure 5). The Differential Encoder effectively transforms an
input data stream into an indication of transitions rather than
1's or 0's. On the decoder side (CS3410), a complementary
Differential Decoder (Figure 6) converts the output from the
Viterbi decoder (transition data) into the original data stream.
Figure 5: Differential Encoder
Figure 6: Differential Decoder
It should be noted that the inclusion of the differential
encoder/decoder elements marginally degrade the error
correcting performance of the core (typical coding gain loss in
Viterbi mode ~0.2 dB). To achieve optimal error correcting
performance, both the differential encoder and decoder
should be bypassed. Therefore, a configuration option is
available for both the CS3310 and CS3410 to by pass
differential encoder/decoder (Core Control register/ADD8).
The CS3410 core is capable of de-puncturing both rate 1/2 and
1/3 symbol streams although its complementary encoder
(CS3310) provides other rates, apart from rate 1/2 and 1/3,
based upon a punctured 1/2 symbol stream. Refer to CS3310
literature regarding the puncture pattern usage. RxERASE
6
CS3410
Data
Coded data
THEORY OF OPERATION
XOR
1 Bit
Delay
High Speed Viterbi/TCM Decoder
1 Bit
Delay
XOR
Coded data
Data
flags mark the deleted bits on the input symbol to the decoder.
For example, when R1ERASE is asserted, the R1 soft decision
vector contribution during branch metric calculation will be
ignored.
Figure 7 represents a typical transmission using QPSK
modulation with its corresponding encoder mapping. Viterbi
rate 1/2 mode is well suited to this type of modulation scheme,
as 1 uncoded bit becomes 2 coded bits when passed through
the Viterbi encoder (CS3310) and QPSK can only transmit one
2-bit symbol at a time.
Figure 7: Encoder Output Mapping for QSPK
Since QPSK is only capable of transmitting one 2-bit symbol at
a time the encoder mapping becomes more complicated when
Viterbi 1/3 is considered. In conjunction with this problem, a
suitable input data interface is provided to enable correct data
alignment for 'in-sync' and 'out-of-sync' conditions. Figure 8
and Figure 9 illustrate the issue of 'out-of-sync' data vectors
thus highlighting the requirement of a suitable data interface.
Figure 8: Data Interface Pattern
Figure 8 demonstrates the intended order of an encoded
sequence for QPSK modulation and transmission. In Viterbi
rate 1/3 mode, output symbols are shared across subsequent
QPSK transmissions. If the receiver/demodulator circuitry is
unable to determine the rotation/phase relationship of the
PSK modulated data, three other rotation positions, illustrated
in Figure 9, may exist.
VitEnc [0]
VitEnc [1]
VitEnc [2]
01
11
I
Q
0
Rate 1/2
1
Q
I
Q
0
2
00
10
I
Q
I
Rate 1/3
I
1
2
Q
Q
I
3