CS3410 Amphion Semiconductor Ltd., CS3410 Datasheet - Page 15

• Manufacturer Part Number: CS3410
• Description: High Speed Viterbi/TCM Decoder
• Manufacturer: Amphion Semiconductor Ltd.

Figure 20: Block Mode Operation
PHASE SYNCHRONIZATION
In both Viterbi and TCM modes of operation, an 'out-of-sync'
condition occurs when a tracked internal path metric state
(most likely path through 'Decision' memory) grows at an
unacceptable 'Normalization' rate. This rate is monitored by
the core's 'Sync Monitor' circuitry. The measurement period
and threshold value that control this measurement are defined
by the core's microprocessor registers, TPERIOD (ADD2/3)
and THRES (ADD4/5). TPERIOD defines the count period
that increments on DVALI. THRES signal defines a threshold
Note
BLKSTARTO
BLKSTARTI
BLKSTOPO
BLKSTOPI
DVALO
: 'out-of-sync' condition triggers correction for these phase angles
RESET
DVALI
CLK
DO
R0
R2
R1
tion Type
Modula-
16-PSK
8-PSK
QPSK
180°, 202.5°, 225°, 247.5°,
270°, 292.5°, 315°, 227.5°
90°, 112.5°, 135°, 157.5°,
180°, 225°, 270°, 315°
0°, 22.5°, 45°, 67.5°,
0°, 90°, 180°, 270°
0°, 45°, 90°, 135°,
Possible Phase
Table 7: Modulation Type vs Phase Shift
Shifts
0°, 45°, 90°, 135°, 180°,
Resolved by Differ-
0°, 90°, 180°, 270°
ential Encoders/
225°, 270°, 315°
value that an accumulated 'Normalization' count value is
compared against. If the THRES value is exceeded when the
count period (TPERIOD) has expired an 'out-of-sync'
condition is flagged. Table 7 summarizes the phase ambiguity
resolution of the core in all modes of operation. For both
Viterbi and TCM modes of operation, input and output
differential blocks, if enabled, automatically compensate for
rotated orthogonal phases. Compensation for other phase
angles is implied once the core is deemed 'out-of-sync'.
Decoder
0°, 180°
157.5°, 202.5°, 247.5°,
45°, 135°, 225°, 315°
Resolved by Phase
22.5°, 67.5°, 112.5°,
292.5°, 337.5°
Ambiguity*
90°, 270°
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TM