T110A103J050AS Kemet Corp., T110A103J050AS Datasheet
T110A103J050AS
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T110A103J050AS Summary of contents
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May 2001, ver. 3.0 Features... Table 1. ACEX TM 1K Device Features Feature Typical gates Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I/O pins Altera Corporation A-DS-ACEX-03.0 Programmable Logic Device Family ® Programmable logic devices ...
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ACEX 1K Programmable Logic Device Family Data Sheet ...and More Features 2 – -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2 for 5.0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry ...
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Table 2. ACEX 1K Package Options & I/O Pin Count Device 100-Pin TQFP EP1K10 66 EP1K30 EP1K50 EP1K100 Notes: (1) ACEX 1K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine BGA packages. ...
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ACEX 1K Programmable Logic Device Family Data Sheet General Description Table 4. ACEX 1K Device Performance Application 16-bit loadable counter 16-bit accumulator 16-to-1 multiplexer (1) 16-bit multiplier with 3-stage pipeline(2) 256 × 16 RAM read cycle speed 256 × 16 ...
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Table 5. ACEX 1K Device Performance for Complex Designs Application 16-bit, 8-tap parallel finite impulse response (FIR) filter 8-bit, 512-point Fast Fourier transform (FFT) function a16450 universal asynchronous receiver/transmitter (UART) Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet ...
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ACEX 1K Programmable Logic Device Family Data Sheet f f Functional Description 6 For more information on the configuration of ACEX 1K devices, see the following documents: I Configuration Devices for ACEX, APEX, FLEX, & Mercury Devices Data Sheet I ...
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Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet The logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect consists of a 4-input LUT, a programmable flipflop, and dedicated ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 1. ACEX 1K Device Block Diagram I/O Element IOE IOE (IOE) IOE IOE Column Interconnect IOE IOE Row Interconnect Logic Array IOE IOE 8 Embedded Array Block (EAB) IOE IOE IOE ...
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Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Embedded Array Block The EAB is a flexible block of RAM, with registers on the input and output ports, that is used to implement common gate array megafunctions. Because it ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 2. ACEX 1K Device in Dual-Port RAM Mode Dedicated Inputs & Global Signals Dedicated Clocks 2 4 data[ ] rdaddress[ ] EAB Local Interconnect (2) wraddress[ ] rden wren outclocken inclocken ...
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Figure 3. ACEX 1K EAB in Dual-Port RAM Mode Clock A Figure 4. ACEX 1K Device in Single-Port RAM Mode Dedicated Inputs & Global Signals Dedicated Clocks 2 EAB Local Interconnect (1) Note: (1) EP1K10, EP1K30, and EP1K50 devices have ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 5. ACEX 1K EAB Memory Configurations 256 × 16 Figure 6. Examples of Combining ACEX 1K EABs 256 × 16 256 × EABs can be used to implement synchronous ...
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Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet If necessary, all EABs in a device can be cascaded to form a single RAM block. EABs can be cascaded to form RAM blocks 2,048 words without ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 7. ACEX 1K LAB (1) LAB Local Interconnect (2) LAB Control Signals Notes: (1) EP1K10, EP1K30, and EP1K50 devices have 22 inputs to the LAB local interconnect channel from the row; ...
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Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Each LAB provides four control signals with programmable inversion that can be used in all eight LEs. Two of these signals can be used as clocks, the other two can ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 8. ACEX 1K Logic Element data1 Look-Up data2 data3 data4 labctrl1 labctrl2 Chip-Wide Reset labctrl3 labctrl4 16 Carry-In Cascade-In Carry Cascade Table Chain Chain (LUT) Clear/ Preset Logic Clock Select Carry-Out ...
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Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Carry Chain The carry chain provides a very fast (as low as 0.2 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order ...
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ACEX 1K Programmable Logic Device Family Data Sheet 18 Figure 9. ACEX 1K Carry Chain Operation (n-Bit Full Adder) Carry-In a1 LUT b1 Carry Chain a2 LUT b2 Carry Chain a n LUT b n Carry Chain LUT Carry Chain ...
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Figure 10. ACEX 1K Cascade Chain Operation AND Cascade Chain d[3..0] d[7..4] d[(4 n – 1)..(4 n – 4)] Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Cascade Chain With the cascade chain, the ACEX 1K architecture can ...
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ACEX 1K Programmable Logic Device Family Data Sheet 20 LE Operating Modes The ACEX 1K LE can operate in the following four modes: I Normal mode I Arithmetic mode I Up/down counter mode I Clearable counter mode Each of these ...
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Figure 11. ACEX 1K LE Operating Modes Normal Mode Carry-In data1 data2 4-Input data3 data4 Arithmetic Mode Carry-In data1 3-Input data2 3-Input Up/Down Counter Mode Carry-In data1 (ena) data2 (u/d) data3 (data) data4 (nload) Clearable Counter Mode Carry-In data1 (ena) ...
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ACEX 1K Programmable Logic Device Family Data Sheet 22 Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the ...
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Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Clearable Counter Mode The clearable counter mode is similar to the up/down counter mode, but it supports a synchronous clear instead of the up/down control. The clear function is substituted ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 12. ACEX 1K LE Clear & Preset Modes Asynchronous Clear VCC PRN D Q CLRN labctrl1 or labctrl2 Chip-Wide Reset Asynchronous Load with Clear NOT labctrl1 (Asynchronous Load) data3 (Data) NOT ...
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Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this mode, the preset signal is tied to VCC to deactivate it. Asynchronous Preset An asynchronous preset ...
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ACEX 1K Programmable Logic Device Family Data Sheet 26 FastTrack Interconnect Routing Structure In the ACEX 1K architecture, connections between LEs, EABs, and device I/O pins are provided by the FastTrack Interconnect routing structure, which is a series of continuous ...
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Figure 13. ACEX 1K LAB Connections to Row & Column Interconnect Row Channels Each LE can drive two row channels Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet At each intersection, six ...
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ACEX 1K Programmable Logic Device Family Data Sheet 28 For improved routing, the row interconnect consists of a combination of full-length and half-length channels. The full-length channels connect to all LABs in a row; the half-length channels connect to the ...
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Figure 14. ACEX 1K Interconnect Resources I/O Element (IOE) IOE IOE Row LAB Interconnect A1 Column Interconnect IOE IOE LAB B1 Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet IOE IOE IOE IOE LAB A2 LAB B2 IOE ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 15. ACEX 1K Bidirectional I/O Registers Row and Column 2 Dedicated Interconnect Clock Inputs Peripheral 4 Dedicated Control Bus Inputs VCC Chip-Wide VCC OE[7..0] Programmable Delay VCC ...
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Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet On all ACEX 1K devices, the input path from the I/O pad to the FastTrack Interconnect has a programmable delay element that can be used to guarantee a zero hold ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 7. Peripheral Bus Sources for ACEX Devices Peripheral Control Signal OE0 OE1 OE2 OE3 OE4 OE5 CLKENA0/CLK0/GLOBAL0 CLKENA1/OE6/GLOBAL1 CLKENA2/CLR0 CLKENA3/OE7/GLOBAL2 CLKENA4/CLR1 CLKENA5/CLK1/GLOBAL3 32 When dedicated inputs drive non-inverted and inverted peripheral ...
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Row-to-IOE Connections When an IOE is used as an input signal, it can drive two separate row channels. The signal is accessible by all LEs within that row. When an IOE is used as an output, the signal is driven ...
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ACEX 1K Programmable Logic Device Family Data Sheet 34 Column-to-IOE Connections When an IOE is used as an input, it can drive up to two separate column channels. When an IOE is used as an output, the signal is driven ...
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SameFrame Pin-Outs Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet ACEX 1K devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA packages such that the ...
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ACEX 1K Programmable Logic Device Family Data Sheet f ClockLock & ClockBoost Features 36 For more information, search for “SameFrame” in MAX+PLUS II Help. Table 10. ACEX 1K SameFrame Pin-Out Support Device EP1K10 EP1K30 EP1K50 EP1K100 Note: (1) This option ...
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Figure 19. Specifications for the Incoming & Generated Clocks Input Clock t R ClockLock Generated Clock Note: (1) The t parameter refers to the nominal input clock period; the t I period. Altera Corporation ACEX 1K Programmable Logic Device Family ...
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ACEX 1K Programmable Logic Device Family Data Sheet Tables 11 for -1 and -2 speed-grade devices, respectively. Table 11. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices Symbol Parameter t Input rise time R t Input fall time F t ...
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Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices Symbol Parameter t Input rise time R t Input fall time F t Input duty cycle INDUTY f Input clock frequency (ClockBoost clock CLK1 multiplication factor equals 1) f Input ...
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ACEX 1K Programmable Logic Device Family Data Sheet 40 PCI Pull-Up Clamping Diode Option ACEX 1K devices have a pull-up clamping diode on every I/O, dedicated input, and dedicated clock pin. PCI clamping diodes clamp the signal to the V ...
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Power Sequencing & Hot-Socketing Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet The VCCINT pins must always be connected to a 2.5-V power supply. With a 2.5-V V level, input voltages are compatible with 2.5-V, 3.3-V, and CCINT ...
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ACEX 1K Programmable Logic Device Family Data Sheet IEEE Std. 1149.1 (JTAG) Boundary-Scan Support Table 14. ACEX 1K JTAG Instructions JTAG Instruction SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during normal device ...
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Table 16. 32-Bit IDCODE for ACEX 1K Devices Device Version (4 Bits) EP1K10 0001 EP1K30 0001 EP1K50 0001 EP1K100 0010 Notes to tables: (1) The most significant bit (MSB the left. (2) The least significant bit (LSB) for ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 20. ACEX 1K JTAG Waveforms TMS TDI TCK TDO Signal to Be Captured Signal to Be Driven 44 t JCP JCH JCL JPSU t t JPZX JPCO t ...
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Generic Testing Operating Conditions Table 18. ACEX 1K Device Absolute Maximum Ratings Symbol Parameter V Supply voltage CCINT V CCIO V DC input voltage output current, per pin OUT T Storage temperature STG T Ambient temperature AMB ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 19. ACEX 1K Device Recommended Operating Conditions Symbol Parameter V Supply voltage for internal logic CCINT and input buffers V Supply voltage for output buffers, CCIO 3.3-V operation Supply voltage for ...
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Table 20. ACEX 1K Device DC Operating Conditions (Part Symbol Parameter V 3.3-V low-level TTL output OL voltage 3.3-V low-level CMOS output voltage 3.3-V low-level PCI output voltage 2.5-V low-level output voltage I I Input pin leakage ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 21. ACEX 1K Device Capacitance Symbol Parameter C Input capacitance IN C Input capacitance on INCLK dedicated clock pin C Output capacitance OUT Notes to tables: (1) See the Operating Requirements ...
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Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Figure 22 shows the required relationship between V satisfy 3.3-V PCI compliance. Figure 22. Relationship between V 2.7 V (V) CCINT II 2.5 2.3 3.0 Figure 23 shows the typical ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 23. Output Drive Characteristics of ACEX 1K Devices Typical Output Current (mA Timing Model ...
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Figure 24. ACEX 1K Device Timing Model Dedicated Clock/Input Figure 25. ACEX 1K Device LE Timing Model Carry-In Data-In Control-In Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Figure 24 shows the overall timing model, which maps the ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 26. ACEX 1K Device IOE Timing Model Data-In Clock Enable Clear Clock Output Enable Feedback Delay Data Feedback into FastTrack Interconnect Figure 27. ACEX 1K Device EAB Timing Model EAB Data ...
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Figure 28. Synchronous Bidirectional Pin External Timing Model Dedicated Clock Figure 29. EAB Asynchronous Timing Waveforms EAB Asynchronous Read WE Address a0 Data-Out d0 EAB Asynchronous Write WE Data-In t EABWASU a0 Address Data-Out Altera Corporation ACEX 1K Programmable Logic ...
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ACEX 1K Programmable Logic Device Family Data Sheet Figure 30. EAB Synchronous Timing Waveforms EAB Synchronous Read WE Address a0 t EABDATASU CLK Data-Out EAB Synchronous Write (EAB Output Registers Used) WE din1 Data- Address t EABWESU CLK ...
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Table 22. LE Timing Microparameters (Part Symbol t Cascade-in to cascade-out delay CASC t LE register control signal delay register clock-to-output delay CO t Combinatorial delay COMB t LE register setup time for data ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 24. EAB Timing Microparameters Symbol t Data or address delay to EAB for combinatorial input EABDATA1 t Data or address delay to EAB for registered input EABDATA2 t Write enable delay ...
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Table 25. EAB Timing Macroparameters Symbol t EAB address access delay EABAA t EAB asynchronous read cycle time EABRCCOMB t EAB synchronous read cycle time EABRCREG t EAB write pulse width EABWP t EAB asynchronous write cycle time EABWCCOMB t ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 26. Interconnect Timing Microparameters Symbol t Delay from dedicated input pin to IOE control input DIN2IOE t Delay from dedicated input pin EAB control input DIN2LE t Delay ...
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Table 27. External Reference Timing Parameters Symbol t Register-to-register delay via four LEs, three row interconnects, and four local DRR interconnects Table 28. External Timing Parameters Symbol t Setup time with global clock at IOE register INSU t Hold time ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 30. EP1K10 Device LE Timing Microparameters Symbol Min t LUT t CLUT t RLUT t PACKED CICO t CGEN t CGENR t CASC ...
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Table 31. EP1K10 Device IOE Timing Microparameters Symbol Min t IOD t IOC t IOCO t IOCOMB t 1.3 IOSU t 0.9 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 32. EP1K10 Device EAB Internal Microparameters Symbol Min t EABDATA1 t EABDATA2 t EABWE1 t EABWE2 t EABRE1 t EABRE2 t EABCLK t EABCO t EABBYPASS t 1.0 EABSU t 0.5 ...
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Table 33. EP1K10 Device EAB Internal Timing Macroparameters Symbol Min t EABAA t 6.7 EABRCCOMB t 4.7 EABRCREG t 2.7 EABWP t 6.4 EABWCCOMB t 7.4 EABWCREG t EABDD t EABDATACO t 1.6 EABDATASU t 0.0 EABDATAH t 1.4 EABWESU ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 34. EP1K10 Device Interconnect Timing Microparameters Symbol Min t DIN2IOE t DIN2LE t DIN2DATA t DCLK2IOE t DCLK2LE t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t ...
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Table 36. EP1K10 External Bidirectional Timing Parameters Symbol Min (2) t 2.2 INSUBIDIR (2) t 0.0 INHBIDIR t (2) 2.0 OUTCOBIDIR t (2) XZBIDIR t (2) ZXBIDIR t (3) 3.1 INSUBIDIR (3) t 0.0 INHBIDIR (3) t 0.5 OUTCOBIDIR (3) ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 37. EP1K30 Device LE Timing Microparameters (Part Symbol Min PRE t CLR t 2 2.0 CL Table 38. EP1K30 ...
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Table 39. EP1K30 Device EAB Internal Microparameters Symbol Min t EABDATA1 t EABDATA1 t EABWE1 t EABWE2 t EABRE1 t EABRE2 t EABCLK t EABCO t EABBYPASS t 0.9 EABSU t 0.4 EABH t 0.3 EABCLR 2.5 ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 40. EP1K30 Device EAB Internal Timing Macroparameters Symbol Min t EABAA t 6.4 EABRCOMB t 4.4 EABRCREG t 2.5 EABWP t 6.0 EABWCOMB t 6.8 EABWCREG t EABDD t EABDATACO t ...
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Table 41. EP1K30 Device Interconnect Timing Microparameters Symbol Min t DIN2IOE t DIN2LE t DIN2DATA t DCLK2IOE t DCLK2LE t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t LABCARRY t LABCASC Table 42. EP1K30 External Timing ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 43. EP1K30 External Bidirectional Timing Parameters Symbol Min t (3) 2.8 INSUBIDIR t (3) 0.0 INHBIDIR t (4) 3.8 INSUBIDIR t (4) 0.0 INHBIDIR t (3) 2.0 OUTCOBIDIR t (3) XZBIDIR ...
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Table 44. EP1K50 Device LE Timing Microparameters (Part Symbol Min COMB PRE t CLR t 2 2.0 CL Table 45. EP1K50 Device IOE Timing Microparameters ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 46. EP1K50 Device EAB Internal Microparameters Symbol Min t EABDATA1 t EABDATA2 t EABWE1 t EABWE2 t EABRE1 t EABRE2 t EABCLK t EABCO t EABBYPASS t 0.7 EABSU t 0.4 ...
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Table 47. EP1K50 Device EAB Internal Timing Macroparameters Symbol Min t EABAA t 3.7 EABRCCOMB t 3.5 EABRCREG t 2.0 EABWP t 4.5 EABWCCOMB t 5.6 EABWCREG t EABDD t EABDATACO t 1.1 EABDATASU t 0.0 EABDATAH t 0.7 EABWESU ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 48. EP1K50 Device Interconnect Timing Microparameters Symbol Min t DIN2IOE t DIN2LE t DIN2DATA t DCLK2IOE t DCLK2LE t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t ...
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Table 50. EP1K50 External Bidirectional Timing Parameters Symbol Min t (2) 2.7 INSUBIDIR t (2) 0.0 INHBIDIR t (3) 3.7 INSUBIDIR t (3) 0.0 INHBIDIR t (2) 2.0 OUTCOBIDIR t (2) XZBIDIR t (2) ZXBIDIR t (3) 0.5 OUTCOBIDIR t ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 51. EP1K100 Device LE Timing Microparameters Symbol Min t LUT t CLUT t RLUT t PACKED CICO t CGEN t CGENR t CASC ...
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Table 52. EP1K100 Device IOE Timing Microparameters Symbol Min t IOD t IOC t IOCO t IOCOMB t 0.8 IOSU t 0.7 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 53. EP1K100 Device EAB Internal Microparameters Symbol Min t EABDATA1 t EABDATA1 t EABWE1 t EABWE2 t EABRE1 t EABRE2 t EABCLK t EABCO t EABBYPASS t 0.8 EABSU t 0.1 ...
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Table 54. EP1K100 Device EAB Internal Timing Macroparameters Symbol Min t EABAA t 5.9 EABRCOMB t 5.1 EABRCREG t 2.7 EABWP t 5.9 EABWCOMB t 5.4 EABWCREG t EABDD t EABDATACO t 0.8 EABDATASU t 0.1 EABDATAH t 1.1 EABWESU ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 55. EP1K100 Device Interconnect Timing Microparameters Symbol Min t DIN2IOE t DIN2LE t DIN2DATA t DCLK2IOE t DCLK2LE t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t ...
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Table 57. EP1K100 External Bidirectional Timing Parameters Symbol Min t (3) 1.7 INSUBIDIR t (3) 0.0 INHBIDIR t (4) 2.0 INSUBIDIR t (4) 0.0 INHBIDIR t (3) 2.0 OUTCOBIDIR t (3) XZBIDIR t (3) ZXBIDIR t (4) 0.5 OUTCOBIDIR t ...
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ACEX 1K Programmable Logic Device Family Data Sheet 82 The I value can be calculated with the following equation: CCACTIVE = K × f × N × tog I CCACTIVE MAX Where Maximum operating frequency in MHz MAX ...
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Figure 31. ACEX 1K I CCACTIVE EP1K30 100 80 Supply Current (mA Configuration & Operation Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet vs. Operating Frequency EP1K50 I CC Current (mA) 100 ...
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ACEX 1K Programmable Logic Device Family Data Sheet Table 59. Data Sources for ACEX 1K Configuration Configuration Scheme Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Passive parallel synchronous (PPS) JTAG Device Pin- Outs 84 During initialization, which occurs ...
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Notes: Altera Corporation ACEX Programmable Logic Family Data Sheet 85 ...
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ACEX 1K Programmable Logic Device Family Data Sheet ® Altera, ACEX, ACEX 1K, APEX, APEX 20K, APEX 20KE, BitBlaster, ByteBlaster, ByteBlasterMV, ClockBoost, 101 Innovation Drive ClockLock, EP1K10, EP1K30, EP1K50, EP1K100, FineLine BGA, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KE, San ...