MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 5

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
N-bit: The N-bit is always set to complement the
L-bit: The L-bit is the DC balancing bit. It is used to
A-bit: The A-bit is used by the NT during line
E-bit: The E-bit is the D-echo channel. The NT will
M-bit: The M-bit establishes the framing pattern for
These bits are collated with the two 64 kbit B-
channels and the 16 kbit D-channel as shown in
Figure 3. This identifies the valid frame structure for
both the NT and the TE.
2.2.1 Terminal Framing
The framing mechanism on the S-interface makes
uses of line code violations to identify frame
boundaries. The F-bit violates the alternating line
code sequence to allow for quick identification of the
frame boundaries. To secure the frame alignment,
another violation of the line code sequence must
occur within 14 bits after the F-bit (refer Figure 4).
The next mark following the frame balancing bit (L-
also be used to identify a multiframe structure
which will make provisions for a low speed
signalling channel to be used in the TE to NT
(Q-channel) or NT to TE (S-channel).
auxiliary framing bit. It is used in conjunction
with the Fa-bit to identify a valid Q-bit.
compensate for DC content on the line. The
balancing bit will be a mark if the preceding
number
balancing bit is odd. The L-bit in the TE to NT
frame
consistent pulse polarity for the first mark of
every B- or D-channel.
activation procedures (refer to Figure 5). The
state of the A-bit will advise the TE if the NT
has achieved synchronization. The A-bit will
be a binary zero (INFO2) if the NT is not
synchronized to the TE and it will bea binary
one (INFO4) if the NT is synchronized
reflect the binary value of the received
D-channel into the transmitted E-bit. The TEs
can thus monitor the D-echo channel to
establish the access contention resolution in
a point-to-multipoint configuration. This is
described in more detail in the section of the
D-channel priority mechanism.
the second level of multiframing which is
used to structure the Q and S bits. The frame
with M-bit=1 identifies frame #1 in the twenty
frame multiframe.
structure
of
marks
will
up
also
to
the
maintain
previous
a
bit) produces this line code violation which will
secure the framing pattern. If the data following the
balancing bit is all binary ones, the zero in the
auxiliary framing bit (Fa) will provide successive
violations to assure that the 14 bit criterion specified
in Recommendation I.430 and ANSI T1.605 are
satisfied.
The state machine used by the SNIC to establish
frame synchronization is as follows. In the power-up
state or in an out-of-sync condition, the terminal
frame synchronization pattern (i.e., violations) must
be received without error for three consecutive
frames. If an invalid framing pattern is received
during the frame search, it will reset the terminal
framer state machine. Upon detection of the third
valid framing pattern, the device will go into a
synchronized state. Once in sync, it will only go out
of sync if three consecutive framing patterns are
received in error. The CCITT I.430 and ANSI T1.605
specifications recommend at least two invalid
framing structures before declaring an out-of-sync
condition. But since the NT can miss a framing
pattern during a multiframe sequence (i.e., idle B1-
channel, Idle D-channel with Q-bit=1), two framing
patterns in error provides very little noise margin.
In a noisy environment, the out-of-sync criteria can
be disabled by selecting the ”force sync” option (B5
of C-channel Control Register). With the force sync
option enabled, the SNIC will lock on to the
boundaries of the received frame thus maintaining a
synchronized state as long as this option is selected.
This function essentially locks the receive counters,
thus the device will not synchronize if the Force Sync
option is enabled during an out-of-sync condition.
2.2.2 Multiframing
The SNIC has provisions for the detection and
generation of the multiframing pattern. This same
multiframe will provide a layer 1 signalling capability
using the S-bit, from NT to TE, and the Q-bit, from
TE to NT.
The multiframe consists of a five S-Bus frame
multiframe. Upon detection of the multiframe signal,
D
Two successive violations identify frame
L
Figure 4 - Framing Pattern
F
L
boundaries
B
B
B
MSAN-141
B
B
B
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