MSC8126 Freescale Semiconductor / Motorola, MSC8126 Datasheet - Page 43

• Manufacturer Part Number: MSC8126
• Description: Quad Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Note:
Note:
3.4
The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of
differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to
assure efficient data transfer across the bus. For example, for 166 MHz operation, you may have to use 183 or 200 MHz
SDRAM. Always perform a detailed timing analysis using the MSC8126 bus timing values and the manufacturer specifications
for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is
usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by
the SDRAM manufacturer.
Freescale Semiconductor
•
•
•
•
— All clock modes are valid in this clock scheme.
See the Clock chapter in the MSC8122 Reference Manual for details.
If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set,
should be pulled up.
The following signals:
used to configure the MSC8126 and are sampled on the deassertion of the
be tied to
When they are used,
be pulled up.
When the Ethernet controller is enabled and the SMII mode is selected,
externally to any signal line.
For details on configuration, see the MSC8126 User’s Guide and MSC8126 Reference Manual. For additional
information, refer to the MSC8126 Design Checklist (AN2903).
– The maximum load on
– Use a zero-delay buffer with a jitter less than 0.3 ns.
External SDRAM Selection
GND
or
V
DDH
INT_OUT
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3]
or through a pull-down or a pull-up resistor until the deassertion of the
(if SIUMCR[INTODC] is cleared),
CLKOUT
must not exceed 10 pF.
NMI_OUT
GPIO10
PPBS
PORESET
, and
can be disconnected. Otherwise, it
IRQxx
and
Hardware Design Considerations
GPIO14
signal. Therefore, they should
,
RSTCONF
(if not full drive) signals must
must not be connected
PORESET
and
BM[0–2]
signal.
are
43